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4bc0104c97
This patch adds support for MediaTek MT7621 SoC. All files are dedicated for u-boot. The default build target is u-boot-mt7621.bin. The specification of this chip: https://www.mediatek.com/products/homenetworking/mt7621 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
154 lines
5.0 KiB
C
154 lines
5.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 MediaTek Inc. All rights reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/mipsregs.h>
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#include <asm/cm.h>
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#include <linux/bitfield.h>
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#include "../mt7621.h"
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/* GIC Shared Register Bases */
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#define GIC_SH_POL_BASE 0x100
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#define GIC_SH_TRIG_BASE 0x180
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#define GIC_SH_RMASK_BASE 0x300
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#define GIC_SH_SMASK_BASE 0x380
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#define GIC_SH_MASK_BASE 0x400
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#define GIC_SH_PEND_BASE 0x480
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#define GIC_SH_MAP_PIN_BASE 0x500
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#define GIC_SH_MAP_VPE_BASE 0x2000
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/* GIC Registers */
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#define GIC_SH_POL31_0 (GIC_SH_POL_BASE + 0x00)
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#define GIC_SH_POL63_32 (GIC_SH_POL_BASE + 0x04)
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#define GIC_SH_TRIG31_0 (GIC_SH_TRIG_BASE + 0x00)
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#define GIC_SH_TRIG63_32 (GIC_SH_TRIG_BASE + 0x04)
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#define GIC_SH_RMASK31_0 (GIC_SH_RMASK_BASE + 0x00)
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#define GIC_SH_RMASK63_32 (GIC_SH_RMASK_BASE + 0x04)
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#define GIC_SH_SMASK31_0 (GIC_SH_SMASK_BASE + 0x00)
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#define GIC_SH_SMASK63_32 (GIC_SH_SMASK_BASE + 0x04)
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#define GIC_SH_MAP_PIN(n) (GIC_SH_MAP_PIN_BASE + (n) * 4)
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#define GIC_SH_MAP_VPE(n, v) (GIC_SH_MAP_VPE_BASE + (n) * 0x20 + ((v) / 32) * 4)
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#define GIC_SH_MAP_VPE31_0(n) GIC_SH_MAP_VPE(n, 0)
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/* GIC_SH_MAP_PIN fields */
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#define GIC_MAP_TO_PIN BIT(31)
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#define GIC_MAP_TO_NMI BIT(30)
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#define GIC_MAP GENMASK(5, 0)
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#define GIC_MAP_SHIFT 0
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static void cm_init(void __iomem *cm_base)
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{
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u32 gcrcfg, num_cores;
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gcrcfg = readl(cm_base + GCR_CONFIG);
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num_cores = FIELD_GET(GCR_CONFIG_PCORES, gcrcfg) + 1;
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writel((1 << num_cores) - 1, cm_base + GCR_ACCESS);
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writel(GCR_REG0_BASE_VALUE, cm_base + GCR_REG0_BASE);
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writel(GCR_REG1_BASE_VALUE, cm_base + GCR_REG1_BASE);
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writel(GCR_REG2_BASE_VALUE, cm_base + GCR_REG2_BASE);
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writel(GCR_REG3_BASE_VALUE, cm_base + GCR_REG3_BASE);
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clrsetbits_32(cm_base + GCR_REG0_MASK,
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GCR_REGn_MASK_ADDRMASK | GCR_REGn_MASK_CMTGT,
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FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG0_MASK_VALUE) |
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GCR_REGn_MASK_CMTGT_IOCU0);
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clrsetbits_32(cm_base + GCR_REG1_MASK,
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GCR_REGn_MASK_ADDRMASK | GCR_REGn_MASK_CMTGT,
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FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG1_MASK_VALUE) |
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GCR_REGn_MASK_CMTGT_IOCU0);
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clrsetbits_32(cm_base + GCR_REG2_MASK,
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GCR_REGn_MASK_ADDRMASK | GCR_REGn_MASK_CMTGT,
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FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG2_MASK_VALUE) |
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GCR_REGn_MASK_CMTGT_IOCU0);
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clrsetbits_32(cm_base + GCR_REG3_MASK,
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GCR_REGn_MASK_ADDRMASK | GCR_REGn_MASK_CMTGT,
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FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG3_MASK_VALUE) |
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GCR_REGn_MASK_CMTGT_IOCU0);
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clrbits_32(cm_base + GCR_BASE, CM_DEFAULT_TARGET_MASK);
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setbits_32(cm_base + GCR_CONTROL, GCR_CONTROL_SYNCCTL);
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}
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static void gic_init(void)
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{
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void __iomem *gic_base = (void *)KSEG1ADDR(MIPS_GIC_BASE);
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int i;
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/* Interrupt 0..5: Level Trigger, Active High */
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writel(0, gic_base + GIC_SH_TRIG31_0);
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writel(0x3f, gic_base + GIC_SH_RMASK31_0);
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writel(0x3f, gic_base + GIC_SH_POL31_0);
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writel(0x3f, gic_base + GIC_SH_SMASK31_0);
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/* Interrupt 56..63: Edge Trigger, Rising Edge */
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/* Hardcoded to set up the last 8 external interrupts for IPI. */
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writel(0xff000000, gic_base + GIC_SH_TRIG63_32);
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writel(0xff000000, gic_base + GIC_SH_RMASK63_32);
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writel(0xff000000, gic_base + GIC_SH_POL63_32);
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writel(0xff000000, gic_base + GIC_SH_SMASK63_32);
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/* Map interrupt source to particular hardware interrupt pin */
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/* source {0,1,2,3,4,5} -> pin {0,0,4,3,0,5} */
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writel(GIC_MAP_TO_PIN | 0, gic_base + GIC_SH_MAP_PIN(0));
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writel(GIC_MAP_TO_PIN | 0, gic_base + GIC_SH_MAP_PIN(1));
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writel(GIC_MAP_TO_PIN | 4, gic_base + GIC_SH_MAP_PIN(2));
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writel(GIC_MAP_TO_PIN | 3, gic_base + GIC_SH_MAP_PIN(3));
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writel(GIC_MAP_TO_PIN | 0, gic_base + GIC_SH_MAP_PIN(4));
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writel(GIC_MAP_TO_PIN | 5, gic_base + GIC_SH_MAP_PIN(5));
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/* source 56~59 -> pin 1, 60~63 -> pin 2 */
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writel(GIC_MAP_TO_PIN | 1, gic_base + GIC_SH_MAP_PIN(56));
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writel(GIC_MAP_TO_PIN | 1, gic_base + GIC_SH_MAP_PIN(57));
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writel(GIC_MAP_TO_PIN | 1, gic_base + GIC_SH_MAP_PIN(58));
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writel(GIC_MAP_TO_PIN | 1, gic_base + GIC_SH_MAP_PIN(59));
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writel(GIC_MAP_TO_PIN | 2, gic_base + GIC_SH_MAP_PIN(60));
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writel(GIC_MAP_TO_PIN | 2, gic_base + GIC_SH_MAP_PIN(61));
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writel(GIC_MAP_TO_PIN | 2, gic_base + GIC_SH_MAP_PIN(62));
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writel(GIC_MAP_TO_PIN | 2, gic_base + GIC_SH_MAP_PIN(63));
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/* Interrupt map to VPE (bit mask) */
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for (i = 0; i < 32; i++)
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writel(BIT(0), gic_base + GIC_SH_MAP_VPE31_0(i));
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/*
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* Direct GIC_int 56..63 to vpe 0..3
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* MIPS Linux convention that last 16 interrupts implemented be set
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* aside for IPI signaling.
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* The actual interrupts are tied low and software sends interrupts
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* via GIC_SH_WEDGE writes.
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*/
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for (i = 0; i < 4; i++) {
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writel(BIT(i), gic_base + GIC_SH_MAP_VPE31_0(i + 56));
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writel(BIT(i), gic_base + GIC_SH_MAP_VPE31_0(i + 60));
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}
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}
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void mt7621_cps_init(void)
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{
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void __iomem *cm_base = (void *)KSEG1ADDR(CONFIG_MIPS_CM_BASE);
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/* Enable GIC */
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writel(MIPS_GIC_BASE | GCR_GIC_EN, cm_base + GCR_GIC_BASE);
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/* Enable CPC */
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writel(MIPS_CPC_BASE | GCR_CPC_EN, cm_base + GCR_CPC_BASE);
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gic_init();
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cm_init(cm_base);
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}
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