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AST2600 has 8 watchdog timers including 8 sets of 32-bit decrement counters, based on 1MHz clock. A 64-bit reset mask is also supported to specify which controllers should be reset by the WDT reset. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
111 lines
2.4 KiB
C
111 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2020 Aspeed Technology, Inc
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <wdt.h>
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#include <asm/io.h>
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#include <asm/arch/wdt_ast2600.h>
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#include <linux/err.h>
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struct ast2600_wdt_priv {
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struct ast2600_wdt *regs;
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};
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static int ast2600_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
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{
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struct ast2600_wdt_priv *priv = dev_get_priv(dev);
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struct ast2600_wdt *wdt = priv->regs;
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/* WDT counts in the 1MHz frequency, namely 1us */
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writel((u32)(timeout_ms * 1000), &wdt->counter_reload_val);
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writel(WDT_COUNTER_RESTART_VAL, &wdt->counter_restart);
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writel(WDT_CTRL_EN | WDT_CTRL_RESET, &wdt->ctrl);
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return 0;
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}
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static int ast2600_wdt_stop(struct udevice *dev)
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{
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struct ast2600_wdt_priv *priv = dev_get_priv(dev);
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struct ast2600_wdt *wdt = priv->regs;
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clrbits_le32(&wdt->ctrl, WDT_CTRL_EN);
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writel(WDT_RESET_MASK1_DEFAULT, &wdt->reset_mask1);
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writel(WDT_RESET_MASK2_DEFAULT, &wdt->reset_mask2);
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return 0;
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}
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static int ast2600_wdt_reset(struct udevice *dev)
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{
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struct ast2600_wdt_priv *priv = dev_get_priv(dev);
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struct ast2600_wdt *wdt = priv->regs;
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writel(WDT_COUNTER_RESTART_VAL, &wdt->counter_restart);
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return 0;
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}
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static int ast2600_wdt_expire_now(struct udevice *dev, ulong flags)
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{
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int ret;
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struct ast2600_wdt_priv *priv = dev_get_priv(dev);
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struct ast2600_wdt *wdt = priv->regs;
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ret = ast2600_wdt_start(dev, 1, flags);
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if (ret)
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return ret;
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while (readl(&wdt->ctrl) & WDT_CTRL_EN)
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;
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return ast2600_wdt_stop(dev);
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}
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static int ast2600_wdt_of_to_plat(struct udevice *dev)
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{
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struct ast2600_wdt_priv *priv = dev_get_priv(dev);
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priv->regs = dev_read_addr_ptr(dev);
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if (!priv->regs)
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return -EINVAL;
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return 0;
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}
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static const struct wdt_ops ast2600_wdt_ops = {
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.start = ast2600_wdt_start,
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.reset = ast2600_wdt_reset,
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.stop = ast2600_wdt_stop,
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.expire_now = ast2600_wdt_expire_now,
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};
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static const struct udevice_id ast2600_wdt_ids[] = {
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{ .compatible = "aspeed,ast2600-wdt" },
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{ }
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};
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static int ast2600_wdt_probe(struct udevice *dev)
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{
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debug("%s() wdt%u\n", __func__, dev_seq(dev));
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ast2600_wdt_stop(dev);
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return 0;
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}
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U_BOOT_DRIVER(ast2600_wdt) = {
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.name = "ast2600_wdt",
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.id = UCLASS_WDT,
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.of_match = ast2600_wdt_ids,
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.probe = ast2600_wdt_probe,
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.priv_auto = sizeof(struct ast2600_wdt_priv),
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.of_to_plat = ast2600_wdt_of_to_plat,
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.ops = &ast2600_wdt_ops,
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};
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