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7a6577fed4
Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
10 lines
134 B
Makefile
10 lines
134 B
Makefile
#
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# Copyright 2021 NXP
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD
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obj-$(CONFIG_IMX8ULP_DRAM) += ddr_init.o
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endif
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