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a38bb0d037
It is useless and misleading to print the ret variable that is not set by the dev_read_addr routine. Also, move the '\n' character after the round bracket that contains the error code. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
128 lines
2.8 KiB
C
128 lines
2.8 KiB
C
#include <common.h>
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#include <ahci.h>
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#include <dm.h>
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#include <log.h>
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#include <scsi.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/delay.h>
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#define AHCI_PHYCS0R 0x00c0
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#define AHCI_PHYCS1R 0x00c4
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#define AHCI_PHYCS2R 0x00c8
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#define AHCI_RWCR 0x00fc
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/* This magic PHY initialisation was taken from the Allwinner releases
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* and Linux driver, but is completely undocumented.
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*/
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static int sunxi_ahci_phy_init(u8 *reg_base)
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{
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u32 reg_val;
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int timeout;
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writel(0, reg_base + AHCI_RWCR);
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mdelay(5);
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setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19);
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clrsetbits_le32(reg_base + AHCI_PHYCS0R,
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(0x7 << 24),
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(0x5 << 24) | (0x1 << 23) | (0x1 << 18));
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clrsetbits_le32(reg_base + AHCI_PHYCS1R,
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(0x3 << 16) | (0x1f << 8) | (0x3 << 6),
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(0x2 << 16) | (0x6 << 8) | (0x2 << 6));
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setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15));
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clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19));
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clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
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clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
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mdelay(5);
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setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
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timeout = 250; /* Power up takes approx 50 us */
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for (;;) {
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reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28);
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if (reg_val == (0x2 << 28))
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break;
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if (--timeout == 0) {
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printf("AHCI PHY power up failed.\n");
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return -EIO;
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}
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udelay(1);
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};
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setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
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timeout = 100; /* Calibration takes approx 10 us */
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for (;;) {
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reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24);
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if (reg_val == 0x0)
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break;
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if (--timeout == 0) {
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printf("AHCI PHY calibration failed.\n");
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return -EIO;
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}
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udelay(1);
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}
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mdelay(15);
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writel(0x7, reg_base + AHCI_RWCR);
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return 0;
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}
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static int sunxi_sata_probe(struct udevice *dev)
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{
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ulong base;
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u8 *reg;
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int ret;
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base = dev_read_addr(dev);
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if (base == FDT_ADDR_T_NONE) {
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debug("%s: Failed to find address\n", __func__);
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return -EINVAL;
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}
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reg = (u8 *)base;
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ret = sunxi_ahci_phy_init(reg);
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if (ret) {
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debug("%s: Failed to init phy (err=%d)\n", __func__, ret);
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return ret;
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}
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ret = ahci_probe_scsi(dev, base);
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if (ret) {
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debug("%s: Failed to probe (err=%d)\n", __func__, ret);
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return ret;
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}
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return 0;
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}
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static int sunxi_sata_bind(struct udevice *dev)
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{
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struct udevice *scsi_dev;
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int ret;
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ret = ahci_bind_scsi(dev, &scsi_dev);
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if (ret) {
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debug("%s: Failed to bind (err=%d)\n", __func__, ret);
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return ret;
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}
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return 0;
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}
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static const struct udevice_id sunxi_ahci_ids[] = {
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{ .compatible = "allwinner,sun4i-a10-ahci" },
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{ .compatible = "allwinner,sun8i-r40-ahci" },
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{ }
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};
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U_BOOT_DRIVER(ahci_sunxi_drv) = {
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.name = "ahci_sunxi",
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.id = UCLASS_AHCI,
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.of_match = sunxi_ahci_ids,
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.bind = sunxi_sata_bind,
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.probe = sunxi_sata_probe,
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};
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