Yu Chien Peter Lin d8a146d19b riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()
As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.

[0] bd7ef41398

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17 19:07:48 +08:00
..
2019-08-15 13:42:28 +08:00
2021-09-07 10:34:29 +08:00
2022-05-26 18:41:21 +08:00
2022-01-19 18:11:34 +01:00
2022-11-03 13:27:56 +08:00
2020-06-25 13:24:10 -04:00