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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
130 lines
2.9 KiB
C
130 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
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*/
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#include <common.h>
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#include <bootstage.h>
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#include <dm.h>
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#include <errno.h>
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#include <init.h>
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#include <timer.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#define CNT_CNTRL_RESET BIT(4)
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struct cadence_ttc_regs {
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u32 clk_cntrl1; /* 0x0 - Clock Control 1 */
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u32 clk_cntrl2; /* 0x4 - Clock Control 2 */
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u32 clk_cntrl3; /* 0x8 - Clock Control 3 */
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u32 counter_cntrl1; /* 0xC - Counter Control 1 */
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u32 counter_cntrl2; /* 0x10 - Counter Control 2 */
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u32 counter_cntrl3; /* 0x14 - Counter Control 3 */
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u32 counter_val1; /* 0x18 - Counter Control 1 */
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u32 counter_val2; /* 0x1C - Counter Control 2 */
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u32 counter_val3; /* 0x20 - Counter Control 3 */
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u32 reserved[15];
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u32 interrupt_enable1; /* 0x60 - Interrupt Enable 1 */
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u32 interrupt_enable2; /* 0x64 - Interrupt Enable 2 */
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u32 interrupt_enable3; /* 0x68 - Interrupt Enable 3 */
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};
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struct cadence_ttc_priv {
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struct cadence_ttc_regs *regs;
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};
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#if CONFIG_IS_ENABLED(BOOTSTAGE)
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ulong timer_get_boot_us(void)
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{
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u64 ticks = 0;
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u32 rate = 1;
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u64 us;
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int ret;
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ret = dm_timer_init();
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if (!ret) {
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/* The timer is available */
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rate = timer_get_rate(gd->timer);
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timer_get_count(gd->timer, &ticks);
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} else {
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return 0;
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}
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us = (ticks * 1000) / rate;
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return us;
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}
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#endif
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static u64 cadence_ttc_get_count(struct udevice *dev)
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{
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struct cadence_ttc_priv *priv = dev_get_priv(dev);
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return readl(&priv->regs->counter_val1);
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}
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static int cadence_ttc_probe(struct udevice *dev)
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{
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struct cadence_ttc_priv *priv = dev_get_priv(dev);
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/* Disable interrupts for sure */
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writel(0, &priv->regs->interrupt_enable1);
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writel(0, &priv->regs->interrupt_enable2);
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writel(0, &priv->regs->interrupt_enable3);
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/* Make sure that clocks are configured properly without prescaller */
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writel(0, &priv->regs->clk_cntrl1);
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writel(0, &priv->regs->clk_cntrl2);
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writel(0, &priv->regs->clk_cntrl3);
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/* Reset and enable this counter */
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writel(CNT_CNTRL_RESET, &priv->regs->counter_cntrl1);
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return 0;
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}
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static int cadence_ttc_of_to_plat(struct udevice *dev)
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{
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struct cadence_ttc_priv *priv = dev_get_priv(dev);
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priv->regs = map_physmem(dev_read_addr(dev),
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sizeof(struct cadence_ttc_regs), MAP_NOCACHE);
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if (IS_ERR(priv->regs))
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return PTR_ERR(priv->regs);
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return 0;
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}
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static int cadence_ttc_bind(struct udevice *dev)
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{
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const char *cells;
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cells = dev_read_prop(dev, "#pwm-cells", NULL);
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if (cells)
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return -ENODEV;
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return 0;
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}
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static const struct timer_ops cadence_ttc_ops = {
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.get_count = cadence_ttc_get_count,
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};
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static const struct udevice_id cadence_ttc_ids[] = {
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{ .compatible = "cdns,ttc" },
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{}
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};
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U_BOOT_DRIVER(cadence_ttc) = {
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.name = "cadence_ttc",
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.id = UCLASS_TIMER,
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.of_match = cadence_ttc_ids,
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.of_to_plat = cadence_ttc_of_to_plat,
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.priv_auto = sizeof(struct cadence_ttc_priv),
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.probe = cadence_ttc_probe,
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.ops = &cadence_ttc_ops,
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.bind = cadence_ttc_bind,
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};
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