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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
124 lines
3.0 KiB
C
124 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 Google LLC
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#define LOG_CATEGORY UCLASS_I2S
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#include <common.h>
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#include <dm.h>
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#include <i2s.h>
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#include <log.h>
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#include <misc.h>
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#include <sound.h>
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#include <asm/io.h>
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#include <asm/arch-tegra/tegra_i2s.h>
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#include "tegra_i2s_priv.h"
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int tegra_i2s_set_cif_tx_ctrl(struct udevice *dev, u32 value)
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{
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struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
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struct i2s_ctlr *regs = (struct i2s_ctlr *)priv->base_address;
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writel(value, ®s->cif_tx_ctrl);
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return 0;
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}
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static void tegra_i2s_transmit_enable(struct i2s_ctlr *regs, int on)
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{
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clrsetbits_le32(®s->ctrl, I2S_CTRL_XFER_EN_TX,
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on ? I2S_CTRL_XFER_EN_TX : 0);
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}
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static int i2s_tx_init(struct i2s_uc_priv *pi2s_tx)
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{
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struct i2s_ctlr *regs = (struct i2s_ctlr *)pi2s_tx->base_address;
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u32 audio_bits = (pi2s_tx->bitspersample >> 2) - 1;
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u32 ctrl = readl(®s->ctrl);
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/* Set format to LRCK / Left Low */
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ctrl &= ~(I2S_CTRL_FRAME_FORMAT_MASK | I2S_CTRL_LRCK_MASK);
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ctrl |= I2S_CTRL_FRAME_FORMAT_LRCK;
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ctrl |= I2S_CTRL_LRCK_L_LOW;
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/* Disable all transmission until we are ready to transfer */
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ctrl &= ~(I2S_CTRL_XFER_EN_TX | I2S_CTRL_XFER_EN_RX);
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/* Serve as master */
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ctrl |= I2S_CTRL_MASTER_ENABLE;
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/* Configure audio bits size */
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ctrl &= ~I2S_CTRL_BIT_SIZE_MASK;
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ctrl |= audio_bits << I2S_CTRL_BIT_SIZE_SHIFT;
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writel(ctrl, ®s->ctrl);
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/* Timing in LRCK mode: */
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writel(pi2s_tx->bitspersample, ®s->timing);
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/* I2S mode has [TX/RX]_DATA_OFFSET both set to 1 */
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writel(((1 << I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
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(1 << I2S_OFFSET_TX_DATA_OFFSET_SHIFT)), ®s->offset);
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/* FSYNC_WIDTH = 2 clocks wide, TOTAL_SLOTS = 2 slots per fsync */
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writel((2 - 1) << I2S_CH_CTRL_FSYNC_WIDTH_SHIFT, ®s->ch_ctrl);
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return 0;
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}
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static int tegra_i2s_tx_data(struct udevice *dev, void *data, uint data_size)
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{
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struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
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struct i2s_ctlr *regs = (struct i2s_ctlr *)priv->base_address;
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int ret;
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tegra_i2s_transmit_enable(regs, 1);
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ret = misc_write(dev_get_parent(dev), 0, data, data_size);
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tegra_i2s_transmit_enable(regs, 0);
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if (ret < 0)
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return ret;
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else if (ret < data_size)
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return -EIO;
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return 0;
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}
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static int tegra_i2s_probe(struct udevice *dev)
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{
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struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
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ulong base;
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base = dev_read_addr(dev);
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if (base == FDT_ADDR_T_NONE) {
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debug("%s: Missing i2s base\n", __func__);
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return -EINVAL;
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}
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priv->base_address = base;
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priv->id = 1;
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priv->audio_pll_clk = 4800000;
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priv->samplingrate = 48000;
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priv->bitspersample = 16;
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priv->channels = 2;
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priv->rfs = 256;
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priv->bfs = 32;
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return i2s_tx_init(priv);
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}
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static const struct i2s_ops tegra_i2s_ops = {
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.tx_data = tegra_i2s_tx_data,
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};
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static const struct udevice_id tegra_i2s_ids[] = {
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{ .compatible = "nvidia,tegra124-i2s" },
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{ }
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};
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U_BOOT_DRIVER(tegra_i2s) = {
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.name = "tegra_i2s",
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.id = UCLASS_I2S,
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.of_match = tegra_i2s_ids,
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.probe = tegra_i2s_probe,
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.ops = &tegra_i2s_ops,
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};
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