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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
254 lines
6.6 KiB
C
254 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <command.h>
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#include <dm.h>
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#include <serial.h>
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#include <watchdog.h>
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#include <asm/cpm_8xx.h>
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#include <asm/global_data.h>
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#include <linux/compiler.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
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#define SMC_INDEX 0
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#define PROFF_SMC PROFF_SMC1
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#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
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#define IOPINS 0xc0
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#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
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#define SMC_INDEX 1
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#define PROFF_SMC PROFF_SMC2
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#define CPM_CR_CH_SMC CPM_CR_CH_SMC2
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#define IOPINS 0xc00
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#endif /* CONFIG_8xx_CONS_SMCx */
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struct serialbuffer {
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cbd_t rxbd; /* Rx BD */
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cbd_t txbd; /* Tx BD */
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uint rxindex; /* index for next character to read */
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uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
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uchar txbuf; /* tx buffers */
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};
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static void serial_setdivisor(cpm8xx_t __iomem *cp, int baudrate)
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{
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int divisor = (gd->cpu_clk + 8 * baudrate) / 16 / baudrate;
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if (divisor / 16 > 0x1000) {
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/* bad divisor, assume 50MHz clock and 9600 baud */
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divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600;
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}
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divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
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if (divisor <= 0x1000)
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out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) | CPM_BRG_EN);
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else
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out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) | CPM_BRG_EN |
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CPM_BRG_DIV16);
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}
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/*
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* Minimal serial functions needed to use one of the SMC ports
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* as serial console interface.
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*/
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static int serial_mpc8xx_setbrg(struct udevice *dev, int baudrate)
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{
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immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
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cpm8xx_t __iomem *cp = &(im->im_cpm);
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/* Set up the baud rate generator.
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* See 8xx_io/commproc.c for details.
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*
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* Wire BRG1 to SMCx
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*/
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out_be32(&cp->cp_simode, 0);
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serial_setdivisor(cp, baudrate);
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return 0;
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}
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static int serial_mpc8xx_probe(struct udevice *dev)
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{
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immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
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smc_t __iomem *sp;
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smc_uart_t __iomem *up;
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u16 smc_rpbase;
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cpm8xx_t __iomem *cp = &(im->im_cpm);
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struct serialbuffer __iomem *rtx;
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/* initialize pointers to SMC */
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sp = cp->cp_smc + SMC_INDEX;
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up = (smc_uart_t __iomem *)&cp->cp_dpmem[PROFF_SMC];
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smc_rpbase = in_be16(&up->smc_rpbase);
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if (smc_rpbase)
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up = (smc_uart_t __iomem *)&cp->cp_dpmem[smc_rpbase];
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/* Disable transmitter/receiver. */
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clrbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
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/* Enable SDMA. */
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out_be32(&im->im_siu_conf.sc_sdcr, 1);
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/* clear error conditions */
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out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);
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/* clear SDMA interrupt mask */
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out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);
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/* Use Port B for SMCx instead of other functions. */
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setbits_be32(&cp->cp_pbpar, IOPINS);
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clrbits_be32(&cp->cp_pbdir, IOPINS);
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clrbits_be16(&cp->cp_pbodr, IOPINS);
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/* Set the physical address of the host memory buffers in
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* the buffer descriptors.
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*/
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rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE];
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/* Allocate space for two buffer descriptors in the DP ram.
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* For now, this address seems OK, but it may have to
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* change with newer versions of the firmware.
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* damm: allocating space after the two buffers for rx/tx data
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*/
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out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf);
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out_be16(&rtx->rxbd.cbd_sc, 0);
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out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf);
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out_be16(&rtx->txbd.cbd_sc, 0);
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/* Set up the uart parameters in the parameter ram. */
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out_be16(&up->smc_rbase, CPM_SERIAL_BASE);
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out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t));
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out_8(&up->smc_rfcr, SMC_EB);
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out_8(&up->smc_tfcr, SMC_EB);
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/* Set UART mode, 8 bit, no parity, one stop.
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* Enable receive and transmit.
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*/
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out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
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/* Mask all interrupts and remove anything pending.
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*/
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out_8(&sp->smc_smcm, 0);
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out_8(&sp->smc_smce, 0xff);
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/* Set up the baud rate generator */
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serial_mpc8xx_setbrg(dev, gd->baudrate);
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/* Make the first buffer the only buffer. */
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setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
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setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
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/* single/multi character receive. */
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out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN);
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out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE);
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out_be32(&rtx->rxindex, 0);
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out_be32(&up->smc_rstate, 0);
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out_be32(&up->smc_tstate, 0);
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out_be16(&up->smc_rbptr, CPM_SERIAL_BASE);
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out_be16(&up->smc_tbptr, CPM_SERIAL_BASE + sizeof(cbd_t));
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out_be16(&up->smc_brkcr, 1);
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out_be16(&up->smc_brkec, 0);
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/* Enable transmitter/receiver. */
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setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
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return 0;
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}
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static int serial_mpc8xx_putc(struct udevice *dev, const char c)
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{
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immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
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cpm8xx_t __iomem *cpmp = &(im->im_cpm);
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struct serialbuffer __iomem *rtx;
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rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
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if (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
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return -EAGAIN;
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out_8(&rtx->txbuf, c);
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out_be16(&rtx->txbd.cbd_datlen, 1);
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setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
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return 0;
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}
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static int serial_mpc8xx_getc(struct udevice *dev)
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{
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immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
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cpm8xx_t __iomem *cpmp = &(im->im_cpm);
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struct serialbuffer __iomem *rtx;
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unsigned char c;
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uint rxindex;
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rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
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if (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
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return -EAGAIN;
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/* the characters are read one by one,
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* use the rxindex to know the next char to deliver
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*/
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rxindex = in_be32(&rtx->rxindex);
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c = in_8(rtx->rxbuf + rxindex);
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rxindex++;
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/* check if all char are readout, then make prepare for next receive */
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if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) {
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rxindex = 0;
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setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
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}
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out_be32(&rtx->rxindex, rxindex);
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return c;
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}
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static int serial_mpc8xx_pending(struct udevice *dev, bool input)
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{
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immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
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cpm8xx_t __iomem *cpmp = &(im->im_cpm);
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struct serialbuffer __iomem *rtx;
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if (!input)
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return 0;
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rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
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return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
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}
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static const struct dm_serial_ops serial_mpc8xx_ops = {
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.putc = serial_mpc8xx_putc,
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.pending = serial_mpc8xx_pending,
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.getc = serial_mpc8xx_getc,
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.setbrg = serial_mpc8xx_setbrg,
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};
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static const struct udevice_id serial_mpc8xx_ids[] = {
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{ .compatible = "fsl,pq1-smc" },
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{ }
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};
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U_BOOT_DRIVER(serial_mpc8xx) = {
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.name = "serial_mpc8xx",
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.id = UCLASS_SERIAL,
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.of_match = serial_mpc8xx_ids,
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.probe = serial_mpc8xx_probe,
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.ops = &serial_mpc8xx_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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