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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
175 lines
3.6 KiB
C
175 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2004-2007 ARM Limited.
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* Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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* Copyright (C) 2015 - 2016 Xilinx, Inc, Michal Simek
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*
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* As a special exception, if other files instantiate templates or use macros
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* or inline functions from this file, or you compile this file and link it
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* with other works to produce a work based on this file, this file does not
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* by itself cause the resulting work to be covered by the GNU General Public
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* License. However the source code for this file must still be made available
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* in accordance with section (3) of the GNU General Public License.
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* This exception does not invalidate any other reasons why a work based on
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* this file might be covered by the GNU General Public License.
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*/
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#include <common.h>
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#include <dm.h>
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#include <serial.h>
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#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7A) || defined(CONFIG_CPU_V7R)
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/*
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* ARMV6 & ARMV7
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*/
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#define DCC_RBIT (1 << 30)
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#define DCC_WBIT (1 << 29)
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#define write_dcc(x) \
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__asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
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#define read_dcc(x) \
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__asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
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#define status_dcc(x) \
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__asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
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#elif defined(CONFIG_CPU_XSCALE)
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/*
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* XSCALE
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*/
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#define DCC_RBIT (1 << 31)
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#define DCC_WBIT (1 << 28)
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#define write_dcc(x) \
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__asm__ volatile ("mcr p14, 0, %0, c8, c0, 0\n" : : "r" (x))
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#define read_dcc(x) \
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__asm__ volatile ("mrc p14, 0, %0, c9, c0, 0\n" : "=r" (x))
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#define status_dcc(x) \
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__asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x))
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#elif defined(CONFIG_ARM64)
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/*
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* ARMV8
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*/
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#define DCC_RBIT (1 << 30)
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#define DCC_WBIT (1 << 29)
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#define write_dcc(x) \
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__asm__ volatile ("msr dbgdtrtx_el0, %0\n" : : "r" (x))
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#define read_dcc(x) \
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__asm__ volatile ("mrs %0, dbgdtrrx_el0\n" : "=r" (x))
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#define status_dcc(x) \
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__asm__ volatile ("mrs %0, mdccsr_el0\n" : "=r" (x))
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#else
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#define DCC_RBIT (1 << 0)
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#define DCC_WBIT (1 << 1)
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#define write_dcc(x) \
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__asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
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#define read_dcc(x) \
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__asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
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#define status_dcc(x) \
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__asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
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#endif
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#define can_read_dcc(x) do { \
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status_dcc(x); \
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x &= DCC_RBIT; \
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} while (0);
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#define can_write_dcc(x) do { \
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status_dcc(x); \
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x &= DCC_WBIT; \
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x = (x == 0); \
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} while (0);
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#define TIMEOUT_COUNT 0x4000000
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static int arm_dcc_getc(struct udevice *dev)
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{
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int ch;
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register unsigned int reg;
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do {
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can_read_dcc(reg);
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} while (!reg);
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read_dcc(ch);
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return ch;
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}
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static int arm_dcc_putc(struct udevice *dev, char ch)
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{
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register unsigned int reg;
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unsigned int timeout_count = TIMEOUT_COUNT;
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while (--timeout_count) {
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can_write_dcc(reg);
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if (reg)
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break;
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}
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if (timeout_count == 0)
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return -EAGAIN;
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else
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write_dcc(ch);
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return 0;
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}
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static int arm_dcc_pending(struct udevice *dev, bool input)
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{
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register unsigned int reg;
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if (input) {
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can_read_dcc(reg);
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} else {
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can_write_dcc(reg);
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}
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return reg;
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}
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static const struct dm_serial_ops arm_dcc_ops = {
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.putc = arm_dcc_putc,
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.pending = arm_dcc_pending,
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.getc = arm_dcc_getc,
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};
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static const struct udevice_id arm_dcc_ids[] = {
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{ .compatible = "arm,dcc", },
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{ }
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};
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U_BOOT_DRIVER(serial_dcc) = {
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.name = "arm_dcc",
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.id = UCLASS_SERIAL,
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.of_match = arm_dcc_ids,
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.ops = &arm_dcc_ops,
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};
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#ifdef CONFIG_DEBUG_UART_ARM_DCC
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#include <debug_uart.h>
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static inline void _debug_uart_init(void)
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{
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}
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static inline void _debug_uart_putc(int ch)
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{
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arm_dcc_putc(NULL, ch);
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}
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DEBUG_UART_FUNCS
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#endif
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