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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
66 lines
1.5 KiB
C
66 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
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*/
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#ifndef __STARFIVE_DDR_H__
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#define __STARFIVE_DDR_H__
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#define SEC_CTRL_ADDR 0x1000
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#define PHY_BASE_ADDR 0x800
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#define PHY_AC_BASE_ADDR 0x1000
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#define DDR_BUS_MASK GENMASK(29, 24)
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#define DDR_AXI_MASK BIT(31)
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#define DDR_BUS_OFFSET 0xAC
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#define DDR_AXI_OFFSET 0xB0
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#define DDR_BUS_OSC_DIV2 0
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#define DDR_BUS_PLL1_DIV2 1
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#define DDR_BUS_PLL1_DIV4 2
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#define DDR_BUS_PLL1_DIV8 3
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#define DDR_AXI_DISABLE 0
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#define DDR_AXI_ENABLE 1
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#define OFFSET_SEL BIT(31)
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#define REG2G BIT(30)
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#define REG4G BIT(29)
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#define REG8G BIT(28)
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#define F_ADDSET BIT(2)
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#define F_SET BIT(1)
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#define F_CLRSET BIT(0)
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#define REGALL (REG2G | REG4G | REG8G)
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#define REGSETALL (F_SET | REGALL)
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#define REGCLRSETALL (F_CLRSET | REGALL)
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#define REGADDSETALL (F_ADDSET | REGALL)
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struct ddr_reg_cfg {
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u32 offset;
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u32 mask;
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u32 val;
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u32 flag;
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};
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enum ddr_size_t {
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DDR_SIZE_2G,
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DDR_SIZE_4G,
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DDR_SIZE_8G,
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DDR_SIZE_16G,
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};
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void ddr_phy_train(u32 *phyreg);
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void ddr_phy_util(u32 *phyreg);
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void ddr_phy_start(u32 *phyreg, enum ddr_size_t size);
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void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size);
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#define DDR_REG_TRIGGER(addr, mask, value) \
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out_le32((addr), (in_le32(addr) & (mask)) | (value))
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#define DDR_REG_SET(type, val) \
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clrsetbits_le32(JH7110_SYS_CRG + DDR_##type##_OFFSET, \
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DDR_##type##_MASK, \
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((val) << __ffs(DDR_##type##_MASK)) & DDR_##type##_MASK)
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#endif /*__STARFIVE_DDR_H__*/
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