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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
123 lines
2.8 KiB
C
123 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Google Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <pwm.h>
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#include <asm/io.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/pwm.h>
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struct exynos_pwm_priv {
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struct s5p_timer *regs;
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};
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static int exynos_pwm_set_config(struct udevice *dev, uint channel,
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uint period_ns, uint duty_ns)
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{
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struct exynos_pwm_priv *priv = dev_get_priv(dev);
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struct s5p_timer *regs = priv->regs;
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unsigned int offset, prescaler;
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uint div = 4, rate, rate_ns;
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u32 val;
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u32 tcnt, tcmp, tcon;
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if (channel >= 5)
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return -EINVAL;
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debug("%s: Configure '%s' channel %u, period_ns %u, duty_ns %u\n",
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__func__, dev->name, channel, period_ns, duty_ns);
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val = readl(®s->tcfg0);
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prescaler = (channel < 2 ? val : (val >> 8)) & 0xff;
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div = (readl(®s->tcfg1) >> MUX_DIV_SHIFT(channel)) & 0xf;
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rate = get_pwm_clk() / ((prescaler + 1) * (1 << div));
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debug("%s: pwm_clk %lu, rate %u\n", __func__, get_pwm_clk(), rate);
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if (channel < 4) {
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rate_ns = 1000000000 / rate;
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tcnt = period_ns / rate_ns;
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tcmp = duty_ns / rate_ns;
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debug("%s: tcnt %u, tcmp %u\n", __func__, tcnt, tcmp);
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/* Ensure that the comparitor will actually hit the target */
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if (tcmp == tcnt)
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tcmp = tcnt - 1;
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offset = channel * 3;
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writel(tcnt, ®s->tcntb0 + offset);
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writel(tcmp, ®s->tcmpb0 + offset);
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}
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tcon = readl(®s->tcon);
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tcon |= TCON_UPDATE(channel);
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if (channel < 4)
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tcon |= TCON_AUTO_RELOAD(channel);
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else
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tcon |= TCON4_AUTO_RELOAD;
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writel(tcon, ®s->tcon);
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tcon &= ~TCON_UPDATE(channel);
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writel(tcon, ®s->tcon);
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return 0;
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}
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static int exynos_pwm_set_enable(struct udevice *dev, uint channel,
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bool enable)
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{
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struct exynos_pwm_priv *priv = dev_get_priv(dev);
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struct s5p_timer *regs = priv->regs;
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u32 mask;
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if (channel >= 4)
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return -EINVAL;
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debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);
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mask = TCON_START(channel);
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clrsetbits_le32(®s->tcon, mask, enable ? mask : 0);
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return 0;
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}
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static int exynos_pwm_probe(struct udevice *dev)
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{
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struct exynos_pwm_priv *priv = dev_get_priv(dev);
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struct s5p_timer *regs = priv->regs;
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writel(PRESCALER_0 | PRESCALER_1 << 8, ®s->tcfg0);
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return 0;
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}
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static int exynos_pwm_of_to_plat(struct udevice *dev)
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{
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struct exynos_pwm_priv *priv = dev_get_priv(dev);
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priv->regs = dev_read_addr_ptr(dev);
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return 0;
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}
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static const struct pwm_ops exynos_pwm_ops = {
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.set_config = exynos_pwm_set_config,
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.set_enable = exynos_pwm_set_enable,
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};
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static const struct udevice_id exynos_channels[] = {
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{ .compatible = "samsung,exynos4210-pwm" },
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{ }
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};
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U_BOOT_DRIVER(exynos_pwm) = {
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.name = "exynos_pwm",
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.id = UCLASS_PWM,
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.of_match = exynos_channels,
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.ops = &exynos_pwm_ops,
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.probe = exynos_pwm_probe,
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.of_to_plat = exynos_pwm_of_to_plat,
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.priv_auto = sizeof(struct exynos_pwm_priv),
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};
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