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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
161 lines
3.6 KiB
C
161 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2013 NVIDIA Corporation
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* Copyright (C) 2018 Cadence Design Systems Inc.
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*/
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#include <common.h>
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#include <div64.h>
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#include <linux/time.h>
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#include <phy-mipi-dphy.h>
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/*
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* Minimum D-PHY timings based on MIPI D-PHY specification. Derived
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* from the valid ranges specified in Section 6.9, Table 14, Page 41
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* of the D-PHY specification (v2.1).
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*/
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int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
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unsigned int bpp,
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unsigned int lanes,
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struct phy_configure_opts_mipi_dphy *cfg)
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{
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unsigned long long hs_clk_rate;
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unsigned long long ui;
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if (!cfg)
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return -EINVAL;
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hs_clk_rate = pixel_clock * bpp;
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do_div(hs_clk_rate, lanes);
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ui = ALIGN(PSEC_PER_SEC, hs_clk_rate);
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do_div(ui, hs_clk_rate);
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cfg->clk_miss = 0;
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cfg->clk_post = 60000 + 52 * ui;
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cfg->clk_pre = 8000;
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cfg->clk_prepare = 38000;
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cfg->clk_settle = 95000;
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cfg->clk_term_en = 0;
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cfg->clk_trail = 60000;
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cfg->clk_zero = 262000;
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cfg->d_term_en = 0;
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cfg->eot = 0;
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cfg->hs_exit = 100000;
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cfg->hs_prepare = 40000 + 4 * ui;
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cfg->hs_zero = 105000 + 6 * ui;
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cfg->hs_settle = 85000 + 6 * ui;
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cfg->hs_skip = 40000;
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/*
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* The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40)
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* contains this formula as:
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*
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* T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui)
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*
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* where n = 1 for forward-direction HS mode and n = 4 for reverse-
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* direction HS mode. There's only one setting and this function does
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* not parameterize on anything other that ui, so this code will
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* assumes that reverse-direction HS mode is supported and uses n = 4.
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*/
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cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui);
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cfg->init = 100;
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cfg->lpx = 60000;
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cfg->ta_get = 5 * cfg->lpx;
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cfg->ta_go = 4 * cfg->lpx;
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cfg->ta_sure = 2 * cfg->lpx;
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cfg->wakeup = 1000;
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cfg->hs_clk_rate = hs_clk_rate;
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cfg->lanes = lanes;
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return 0;
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}
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/*
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* Validate D-PHY configuration according to MIPI D-PHY specification
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* (v1.2, Section Section 6.9 "Global Operation Timing Parameters").
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*/
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int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg)
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{
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unsigned long long ui;
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if (!cfg)
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return -EINVAL;
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ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate);
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do_div(ui, cfg->hs_clk_rate);
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if (cfg->clk_miss > 60000)
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return -EINVAL;
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if (cfg->clk_post < (60000 + 52 * ui))
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return -EINVAL;
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if (cfg->clk_pre < 8000)
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return -EINVAL;
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if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000)
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return -EINVAL;
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if (cfg->clk_settle < 95000 || cfg->clk_settle > 300000)
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return -EINVAL;
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if (cfg->clk_term_en > 38000)
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return -EINVAL;
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if (cfg->clk_trail < 60000)
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return -EINVAL;
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if ((cfg->clk_prepare + cfg->clk_zero) < 300000)
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return -EINVAL;
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if (cfg->d_term_en > (35000 + 4 * ui))
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return -EINVAL;
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if (cfg->eot > (105000 + 12 * ui))
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return -EINVAL;
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if (cfg->hs_exit < 100000)
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return -EINVAL;
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if (cfg->hs_prepare < (40000 + 4 * ui) ||
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cfg->hs_prepare > (85000 + 6 * ui))
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return -EINVAL;
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if ((cfg->hs_prepare + cfg->hs_zero) < (145000 + 10 * ui))
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return -EINVAL;
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if ((cfg->hs_settle < (85000 + 6 * ui)) ||
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(cfg->hs_settle > (145000 + 10 * ui)))
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return -EINVAL;
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if (cfg->hs_skip < 40000 || cfg->hs_skip > (55000 + 4 * ui))
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return -EINVAL;
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if (cfg->hs_trail < max(8 * ui, 60000 + 4 * ui))
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return -EINVAL;
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if (cfg->init < 100)
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return -EINVAL;
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if (cfg->lpx < 50000)
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return -EINVAL;
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if (cfg->ta_get != (5 * cfg->lpx))
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return -EINVAL;
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if (cfg->ta_go != (4 * cfg->lpx))
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return -EINVAL;
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if (cfg->ta_sure < cfg->lpx || cfg->ta_sure > (2 * cfg->lpx))
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return -EINVAL;
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if (cfg->wakeup < 1000)
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return -EINVAL;
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return 0;
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}
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