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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
118 lines
3.4 KiB
C
118 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* PLDA XpressRich PCIe host controller common functions.
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*
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* Copyright (C) 2023 StarFive Technology Co., Ltd.
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*
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include "pcie_plda_common.h"
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static bool plda_pcie_addr_valid(struct pcie_plda *plda, pci_dev_t bdf)
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{
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/*
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* Single device limitation.
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* PCIe controller contain HW issue that secondary bus of
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* host bridge emumerate duplicate devices.
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* Only can access device 0 in secondary bus.
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*/
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if (PCI_BUS(bdf) == plda->sec_busno && PCI_DEV(bdf) > 0)
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return false;
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return true;
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}
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static int plda_pcie_conf_address(const struct udevice *udev, pci_dev_t bdf,
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uint offset, void **paddr)
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{
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struct pcie_plda *priv = dev_get_priv(udev);
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int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf) - dev_seq(udev),
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PCI_DEV(bdf), PCI_FUNC(bdf), offset);
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if (!plda_pcie_addr_valid(priv, bdf))
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return -ENODEV;
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*paddr = (void *)(priv->cfg_base + where);
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return 0;
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}
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int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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return pci_generic_mmap_read_config(udev, plda_pcie_conf_address,
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bdf, offset, valuep, size);
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}
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int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct pcie_plda *priv = dev_get_priv(udev);
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int ret;
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ret = pci_generic_mmap_write_config(udev, plda_pcie_conf_address,
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bdf, offset, value, size);
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/* record secondary bus number */
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if (!ret && PCI_BUS(bdf) == dev_seq(udev) &&
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PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
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(offset == PCI_SECONDARY_BUS ||
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(offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))) {
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priv->sec_busno =
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((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value) & 0xff;
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priv->sec_busno += dev_seq(udev);
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debug("Secondary bus number was changed to %d\n",
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priv->sec_busno);
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}
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return ret;
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}
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int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
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phys_addr_t trsl_addr, phys_size_t window_size,
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int trsl_param)
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{
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void __iomem *base =
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plda->reg_base + XR3PCI_ATR_AXI4_SLV0;
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/* Support AXI4 Slave 0 Address Translation Tables 0-7. */
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if (plda->atr_table_num >= XR3PCI_ATR_MAX_TABLE_NUM) {
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dev_err(plda->dev, "ATR table number %d exceeds max num\n",
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plda->atr_table_num);
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return -EINVAL;
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}
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base += XR3PCI_ATR_TABLE_OFFSET * plda->atr_table_num;
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plda->atr_table_num++;
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/*
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* X3PCI_ATR_SRC_ADDR_LOW:
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* - bit 0: enable entry,
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* - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
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* - bits 7-11: reserved
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* - bits 12-31: start of source address
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*/
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writel((lower_32_bits(src_addr) & XR3PCI_ATR_SRC_ADDR_MASK) |
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(fls(window_size) - 1) << XR3PCI_ATR_SRC_WIN_SIZE_SHIFT | 1,
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base + XR3PCI_ATR_SRC_ADDR_LOW);
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writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH);
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writel((lower_32_bits(trsl_addr) & XR3PCI_ATR_TRSL_ADDR_MASK),
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base + XR3PCI_ATR_TRSL_ADDR_LOW);
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writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
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writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
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dev_dbg(plda->dev, "ATR entry: 0x%010llx %s 0x%010llx [0x%010llx] (param: 0x%06x)\n",
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src_addr, (trsl_param & XR3PCI_ATR_TRSL_DIR) ? "<-" : "->",
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trsl_addr, (u64)window_size, trsl_param);
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return 0;
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}
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