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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
127 lines
3.4 KiB
C
127 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Cortina CS4315/CS4340 10G PHY drivers
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*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Copyright 2018 NXP
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*
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*/
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#include <config.h>
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#include <common.h>
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#include <log.h>
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#include <malloc.h>
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#include <linux/ctype.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/err.h>
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#include <phy.h>
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#define PHY_ID_RTL8211_EXT 0x001cc910
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#define PHY_ID_RTL8211_INT 0x001cc980
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#define PHY_ID_MASK 0xFFFFFFF0
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static void __internal_phy_init(struct phy_device *phydev, int reset_phy)
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{
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u8 phy_addr;
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u16 data;
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/* should initialize 4 GPHYs at once */
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for (phy_addr = 4; phy_addr > 0; phy_addr--) {
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phydev->addr = phy_addr;
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phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0BC6);
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phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x0053);
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phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x4003);
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phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x7e01);
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phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0A42);
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phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0A40);
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phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x1140);
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}
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/* workaround to fix GPHY fail */
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for (phy_addr = 1; phy_addr < 5; phy_addr++) {
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/* Clear clock fail interrupt */
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phydev->addr = phy_addr;
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phy_write(phydev, MDIO_DEVAD_NONE, 31, 0xB90);
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data = phy_read(phydev, MDIO_DEVAD_NONE, 19);
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if (data == 0x10) {
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phy_write(phydev, MDIO_DEVAD_NONE, 31, 0xB90);
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data = phy_read(phydev, MDIO_DEVAD_NONE, 19);
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printf("%s: read again.\n", __func__);
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}
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printf("%s: phy_addr=%d, read register 19, value=0x%x\n",
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__func__, phy_addr, data);
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}
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}
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static void __external_phy_init(struct phy_device *phydev, int reset_phy)
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{
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u16 val;
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/* Disable response PHYAD=0 function of RTL8211 series PHY */
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/* REG31 write 0x0007, set to extension page */
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phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0007);
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/* REG30 write 0x002C, set to extension page 44 */
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phy_write(phydev, MDIO_DEVAD_NONE, 30, 0x002C);
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/*
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* REG27 write bit[2] = 0 disable response PHYAD = 0 function.
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* we should read REG27 and clear bit[2], and write back
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*/
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val = phy_read(phydev, MDIO_DEVAD_NONE, 27);
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val &= ~(1 << 2);
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phy_write(phydev, MDIO_DEVAD_NONE, 27, val);
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/* REG31 write 0X0000, back to page0 */
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phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
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}
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static int rtl8211_external_config(struct phy_device *phydev)
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{
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__external_phy_init(phydev, 0);
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printf("%s: initialize RTL8211 external done.\n", __func__);
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return 0;
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}
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static int rtl8211_internal_config(struct phy_device *phydev)
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{
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struct phy_device phydev_init;
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memcpy(&phydev_init, phydev, sizeof(struct phy_device));
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/* should initialize 4 GPHYs at once */
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__internal_phy_init(&phydev_init, 0);
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printf("%s: initialize RTL8211 internal done.\n", __func__);
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return 0;
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}
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static int rtl8211_probe(struct phy_device *phydev)
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{
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/* disable reset behavior */
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phydev->flags = PHY_FLAG_BROKEN_RESET;
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return 0;
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}
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/* Support for RTL8211 External PHY */
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U_BOOT_PHY_DRIVER(rtl8211_external) = {
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.name = "Cortina RTL8211 External",
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.uid = PHY_ID_RTL8211_EXT,
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.mask = PHY_ID_MASK,
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.features = PHY_GBIT_FEATURES,
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.config = &rtl8211_external_config,
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.probe = &rtl8211_probe,
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.startup = &genphy_startup,
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};
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/* Support for RTL8211 Internal PHY */
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U_BOOT_PHY_DRIVER(rtl8211_internal) = {
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.name = "Cortina RTL8211 Inrernal",
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.uid = PHY_ID_RTL8211_INT,
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.mask = PHY_ID_MASK,
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.features = PHY_GBIT_FEATURES,
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.config = &rtl8211_internal_config,
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.probe = &rtl8211_probe,
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.startup = &genphy_startup,
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};
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