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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
126 lines
3.0 KiB
C
126 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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* Andy Fleming <afleming@gmail.com>
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* Some part is taken from tsec.c
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <fsl_tgec.h>
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#include <fm_eth.h>
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/*
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* Write value to the PHY for this device to the register at regnum, waiting
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* until the write is done before it returns. All PHY configuration has to be
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* done through the TSEC1 MIIM regs
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*/
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static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
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int regnum, u16 value)
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{
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u32 mdio_ctl;
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u32 stat_val;
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struct tgec_mdio_controller *regs = bus->priv;
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if (dev_addr == MDIO_DEVAD_NONE)
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return 0;
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/* Wait till the bus is free */
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stat_val = MDIO_STAT_CLKDIV(100);
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out_be32(®s->mdio_stat, stat_val);
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Set the port and dev addr */
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mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
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out_be32(®s->mdio_ctl, mdio_ctl);
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/* Set the register address */
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out_be32(®s->mdio_addr, regnum & 0xffff);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Write the value to the register */
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out_be32(®s->mdio_data, MDIO_DATA(value));
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/* Wait till the MDIO write is complete */
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while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
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;
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return 0;
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}
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/*
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* Reads from register regnum in the PHY for device dev, returning the value.
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* Clears miimcom first. All PHY configuration has to be done through the
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* TSEC1 MIIM regs
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*/
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static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
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int regnum)
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{
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u32 mdio_ctl;
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u32 stat_val;
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struct tgec_mdio_controller *regs = bus->priv;
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if (dev_addr == MDIO_DEVAD_NONE)
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return 0xffff;
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stat_val = MDIO_STAT_CLKDIV(100);
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out_be32(®s->mdio_stat, stat_val);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Set the Port and Device Addrs */
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mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
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out_be32(®s->mdio_ctl, mdio_ctl);
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/* Set the register address */
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out_be32(®s->mdio_addr, regnum & 0xffff);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Initiate the read */
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mdio_ctl |= MDIO_CTL_READ;
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out_be32(®s->mdio_ctl, mdio_ctl);
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/* Wait till the MDIO write is complete */
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while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
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;
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/* Return all Fs if nothing was there */
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if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER)
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return 0xffff;
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return in_be32(®s->mdio_data) & 0xffff;
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}
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static int tgec_mdio_reset(struct mii_dev *bus)
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{
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return 0;
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}
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int fm_tgec_mdio_init(struct bd_info *bis, struct tgec_mdio_info *info)
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{
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate FM TGEC MDIO bus\n");
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return -1;
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}
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bus->read = tgec_mdio_read;
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bus->write = tgec_mdio_write;
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bus->reset = tgec_mdio_reset;
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strcpy(bus->name, info->name);
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bus->priv = info->regs;
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return mdio_register(bus);
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}
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