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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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u32 port_to_devdisr[] = {
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[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
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[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
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[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
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[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
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[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
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[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
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[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
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[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
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[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
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[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
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[FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
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[FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
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};
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static int is_device_disabled(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
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u32 devdisr2 = in_be32(&gur->devdisr2);
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return port_to_devdisr[port] & devdisr2;
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}
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void fman_disable_port(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
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/* don't allow disabling of DTSEC1 as its needed for MDIO */
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if (port == FM1_DTSEC1)
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return;
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setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
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}
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void fman_enable_port(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
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clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
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}
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phy_interface_t fman_port_enet_if(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
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u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
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if (is_device_disabled(port))
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return PHY_INTERFACE_MODE_NA;
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if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
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return PHY_INTERFACE_MODE_XGMII;
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if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
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return PHY_INTERFACE_MODE_XGMII;
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/* handle RGMII first */
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if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
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FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII))
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return PHY_INTERFACE_MODE_RGMII;
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if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
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FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII))
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return PHY_INTERFACE_MODE_MII;
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if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
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FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII))
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return PHY_INTERFACE_MODE_RGMII;
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if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
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FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII))
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return PHY_INTERFACE_MODE_MII;
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switch (port) {
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case FM1_DTSEC1:
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case FM1_DTSEC2:
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case FM1_DTSEC3:
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case FM1_DTSEC4:
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case FM1_DTSEC5:
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if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
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return PHY_INTERFACE_MODE_SGMII;
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break;
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case FM2_DTSEC1:
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case FM2_DTSEC2:
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case FM2_DTSEC3:
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case FM2_DTSEC4:
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case FM2_DTSEC5:
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if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
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return PHY_INTERFACE_MODE_SGMII;
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break;
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default:
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return PHY_INTERFACE_MODE_NA;
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}
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return PHY_INTERFACE_MODE_NA;
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}
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