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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
93 lines
1.9 KiB
C
93 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#include <common.h>
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#include <linux/mtd/rawnand.h>
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#include <asm/io.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <nand.h>
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/* NAND Flash Soc registers */
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struct kwnandf_registers {
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u32 rd_params; /* 0x10418 */
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u32 wr_param; /* 0x1041c */
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u8 pad[0x10470 - 0x1041c - 4];
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u32 ctrl; /* 0x10470 */
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};
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static struct kwnandf_registers *nf_reg =
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(struct kwnandf_registers *)KW_NANDF_BASE;
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static u32 nand_mpp_backup[9] = { 0 };
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/*
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* hardware specific access to control-lines/bits
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*/
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#define NAND_ACTCEBOOT_BIT 0x02
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static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *nc = mtd_to_nand(mtd);
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u32 offs;
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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offs = (1 << 0); /* Commands with A[1:0] == 01 */
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else if (ctrl & NAND_ALE)
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offs = (1 << 1); /* Addresses with A[1:0] == 10 */
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else
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return;
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writeb(cmd, nc->IO_ADDR_W + offs);
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}
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void kw_nand_select_chip(struct mtd_info *mtd, int chip)
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{
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u32 data;
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static const u32 nand_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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0
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};
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if (chip >= 0)
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kirkwood_mpp_conf(nand_config, nand_mpp_backup);
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else
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kirkwood_mpp_conf(nand_mpp_backup, NULL);
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data = readl(&nf_reg->ctrl);
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data |= NAND_ACTCEBOOT_BIT;
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writel(data, &nf_reg->ctrl);
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}
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int board_nand_init(struct nand_chip *nand)
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{
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nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
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#if defined(CONFIG_SYS_NAND_NO_SUBPAGE_WRITE)
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nand->options |= NAND_NO_SUBPAGE_WRITE;
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#endif
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#if defined(CONFIG_NAND_ECC_BCH)
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nand->ecc.mode = NAND_ECC_SOFT_BCH;
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#else
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nand->ecc.mode = NAND_ECC_SOFT;
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#endif
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nand->cmd_ctrl = kw_nand_hwcontrol;
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nand->chip_delay = 40;
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nand->select_chip = kw_nand_select_chip;
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return 0;
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}
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