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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
350 lines
8.1 KiB
C
350 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* eFuse driver for Rockchip devices
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*
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* Copyright 2017, Theobroma Systems Design und Consulting GmbH
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* Written by Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <command.h>
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#include <display_options.h>
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#include <dm.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <malloc.h>
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#include <misc.h>
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#define EFUSE_CTRL 0x0000
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#define RK3036_A_SHIFT 8
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#define RK3036_A_MASK GENMASK(15, 8)
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#define RK3036_ADDR(n) ((n) << RK3036_A_SHIFT)
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#define RK3128_A_SHIFT 7
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#define RK3128_A_MASK GENMASK(15, 7)
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#define RK3128_ADDR(n) ((n) << RK3128_A_SHIFT)
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#define RK3288_A_SHIFT 6
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#define RK3288_A_MASK GENMASK(15, 6)
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#define RK3288_ADDR(n) ((n) << RK3288_A_SHIFT)
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#define RK3399_A_SHIFT 16
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#define RK3399_A_MASK GENMASK(25, 16)
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#define RK3399_ADDR(n) ((n) << RK3399_A_SHIFT)
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#define RK3399_STROBSFTSEL BIT(9)
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#define RK3399_RSB BIT(7)
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#define RK3399_PD BIT(5)
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#define EFUSE_PGENB BIT(3)
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#define EFUSE_LOAD BIT(2)
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#define EFUSE_STROBE BIT(1)
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#define EFUSE_CSB BIT(0)
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#define EFUSE_DOUT 0x0004
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#define RK3328_INT_STATUS 0x0018
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#define RK3328_INT_FINISH BIT(0)
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#define RK3328_DOUT 0x0020
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#define RK3328_AUTO_CTRL 0x0024
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#define RK3328_AUTO_RD BIT(1)
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#define RK3328_AUTO_ENB BIT(0)
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struct rockchip_efuse_plat {
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void __iomem *base;
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};
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struct rockchip_efuse_data {
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int (*read)(struct udevice *dev, int offset, void *buf, int size);
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int offset;
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int size;
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int block_size;
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};
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#if defined(DEBUG)
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static int dump_efuse(struct cmd_tbl *cmdtp, int flag,
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int argc, char *const argv[])
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{
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struct udevice *dev;
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u8 data[4];
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int ret, i;
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_DRIVER_GET(rockchip_efuse), &dev);
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if (ret) {
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printf("%s: no misc-device found\n", __func__);
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return 0;
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}
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for (i = 0; true; i += sizeof(data)) {
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ret = misc_read(dev, i, &data, sizeof(data));
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if (ret <= 0)
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return 0;
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print_buffer(i, data, 1, sizeof(data), sizeof(data));
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}
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return 0;
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}
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U_BOOT_CMD(
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dump_efuse, 1, 1, dump_efuse,
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"Dump the content of the efuse",
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""
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);
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#endif
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static int rockchip_rk3036_efuse_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct rockchip_efuse_plat *efuse = dev_get_plat(dev);
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u8 *buffer = buf;
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/* Switch to read mode */
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writel(EFUSE_LOAD, efuse->base + EFUSE_CTRL);
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udelay(2);
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while (size--) {
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clrsetbits_le32(efuse->base + EFUSE_CTRL, RK3036_A_MASK,
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RK3036_ADDR(offset++));
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udelay(2);
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setbits_le32(efuse->base + EFUSE_CTRL, EFUSE_STROBE);
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udelay(2);
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*buffer++ = (u8)(readl(efuse->base + EFUSE_DOUT) & 0xFF);
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clrbits_le32(efuse->base + EFUSE_CTRL, EFUSE_STROBE);
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udelay(2);
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}
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/* Switch to inactive mode */
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writel(0x0, efuse->base + EFUSE_CTRL);
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return 0;
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}
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static int rockchip_rk3128_efuse_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct rockchip_efuse_plat *efuse = dev_get_plat(dev);
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u8 *buffer = buf;
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/* Switch to read mode */
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writel(EFUSE_LOAD, efuse->base + EFUSE_CTRL);
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udelay(2);
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while (size--) {
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clrsetbits_le32(efuse->base + EFUSE_CTRL, RK3128_A_MASK,
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RK3128_ADDR(offset++));
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udelay(2);
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setbits_le32(efuse->base + EFUSE_CTRL, EFUSE_STROBE);
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udelay(2);
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*buffer++ = (u8)(readl(efuse->base + EFUSE_DOUT) & 0xFF);
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clrbits_le32(efuse->base + EFUSE_CTRL, EFUSE_STROBE);
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udelay(2);
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}
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/* Switch to inactive mode */
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writel(0x0, efuse->base + EFUSE_CTRL);
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return 0;
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}
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static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct rockchip_efuse_plat *efuse = dev_get_plat(dev);
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u8 *buffer = buf;
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/* Switch to read mode */
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writel(EFUSE_CSB, efuse->base + EFUSE_CTRL);
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writel(EFUSE_LOAD | EFUSE_PGENB, efuse->base + EFUSE_CTRL);
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udelay(2);
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while (size--) {
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clrsetbits_le32(efuse->base + EFUSE_CTRL, RK3288_A_MASK,
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RK3288_ADDR(offset++));
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udelay(2);
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setbits_le32(efuse->base + EFUSE_CTRL, EFUSE_STROBE);
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udelay(2);
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*buffer++ = (u8)(readl(efuse->base + EFUSE_DOUT) & 0xFF);
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clrbits_le32(efuse->base + EFUSE_CTRL, EFUSE_STROBE);
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udelay(2);
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}
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/* Switch to standby mode */
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writel(EFUSE_CSB | EFUSE_PGENB, efuse->base + EFUSE_CTRL);
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return 0;
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}
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static int rockchip_rk3328_efuse_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct rockchip_efuse_plat *efuse = dev_get_plat(dev);
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u32 status, *buffer = buf;
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int ret;
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while (size--) {
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writel(RK3328_AUTO_RD | RK3328_AUTO_ENB | RK3399_ADDR(offset++),
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efuse->base + RK3328_AUTO_CTRL);
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udelay(1);
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ret = readl_poll_sleep_timeout(efuse->base + RK3328_INT_STATUS,
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status, (status & RK3328_INT_FINISH), 1, 50);
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if (ret)
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return ret;
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*buffer++ = readl(efuse->base + RK3328_DOUT);
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writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS);
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}
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return 0;
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}
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static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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struct rockchip_efuse_plat *efuse = dev_get_plat(dev);
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u32 *buffer = buf;
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/* Switch to array read mode */
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writel(EFUSE_LOAD | EFUSE_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
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efuse->base + EFUSE_CTRL);
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udelay(1);
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while (size--) {
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setbits_le32(efuse->base + EFUSE_CTRL,
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EFUSE_STROBE | RK3399_ADDR(offset++));
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udelay(1);
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*buffer++ = readl(efuse->base + EFUSE_DOUT);
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clrbits_le32(efuse->base + EFUSE_CTRL, EFUSE_STROBE);
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udelay(1);
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}
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/* Switch to power-down mode */
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writel(RK3399_PD | EFUSE_CSB, efuse->base + EFUSE_CTRL);
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return 0;
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}
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static int rockchip_efuse_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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const struct rockchip_efuse_data *data =
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(void *)dev_get_driver_data(dev);
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u32 block_start, block_end, block_offset, blocks;
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u8 *buffer;
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int ret;
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if (offset < 0 || !buf || size <= 0 || offset + size > data->size)
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return -EINVAL;
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if (!data->read)
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return -ENOSYS;
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offset += data->offset;
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if (data->block_size <= 1) {
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ret = data->read(dev, offset, buf, size);
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goto done;
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}
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block_start = offset / data->block_size;
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block_offset = offset % data->block_size;
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block_end = DIV_ROUND_UP(offset + size, data->block_size);
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blocks = block_end - block_start;
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buffer = calloc(blocks, data->block_size);
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if (!buffer)
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return -ENOMEM;
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ret = data->read(dev, block_start, buffer, blocks);
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if (!ret)
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memcpy(buf, buffer + block_offset, size);
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free(buffer);
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done:
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return ret < 0 ? ret : size;
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}
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static const struct misc_ops rockchip_efuse_ops = {
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.read = rockchip_efuse_read,
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};
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static int rockchip_efuse_of_to_plat(struct udevice *dev)
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{
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struct rockchip_efuse_plat *plat = dev_get_plat(dev);
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plat->base = dev_read_addr_ptr(dev);
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return 0;
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}
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static const struct rockchip_efuse_data rk3036_data = {
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.read = rockchip_rk3036_efuse_read,
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.size = 0x20,
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};
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static const struct rockchip_efuse_data rk3128_data = {
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.read = rockchip_rk3128_efuse_read,
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.size = 0x40,
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};
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static const struct rockchip_efuse_data rk3288_data = {
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.read = rockchip_rk3288_efuse_read,
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.size = 0x20,
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};
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static const struct rockchip_efuse_data rk3328_data = {
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.read = rockchip_rk3328_efuse_read,
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.offset = 0x60,
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.size = 0x20,
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.block_size = 4,
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};
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static const struct rockchip_efuse_data rk3399_data = {
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.read = rockchip_rk3399_efuse_read,
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.size = 0x80,
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.block_size = 4,
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};
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static const struct udevice_id rockchip_efuse_ids[] = {
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{
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.compatible = "rockchip,rk3036-efuse",
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.data = (ulong)&rk3036_data,
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},
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{
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.compatible = "rockchip,rk3066a-efuse",
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.data = (ulong)&rk3288_data,
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},
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{
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.compatible = "rockchip,rk3128-efuse",
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.data = (ulong)&rk3128_data,
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},
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{
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.compatible = "rockchip,rk3188-efuse",
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.data = (ulong)&rk3288_data,
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},
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{
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.compatible = "rockchip,rk3228-efuse",
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.data = (ulong)&rk3288_data,
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},
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{
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.compatible = "rockchip,rk3288-efuse",
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.data = (ulong)&rk3288_data,
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},
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{
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.compatible = "rockchip,rk3328-efuse",
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.data = (ulong)&rk3328_data,
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},
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{
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.compatible = "rockchip,rk3399-efuse",
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.data = (ulong)&rk3399_data,
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},
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{}
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};
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U_BOOT_DRIVER(rockchip_efuse) = {
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.name = "rockchip_efuse",
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.id = UCLASS_MISC,
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.of_match = rockchip_efuse_ids,
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.of_to_plat = rockchip_efuse_of_to_plat,
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.plat_auto = sizeof(struct rockchip_efuse_plat),
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.ops = &rockchip_efuse_ops,
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};
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