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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
124 lines
3.0 KiB
C
124 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2022 Nuvoton Technology Corp.
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/gpio.h>
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#include <linux/io.h>
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#define NPCM_GPIOS_PER_BANK 32
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/* Register offsets */
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#define GPIO_DIN 0x4 /* RO - Data In */
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#define GPIO_DOUT 0xC /* RW - Data Out */
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#define GPIO_OE 0x10 /* RW - Output Enable */
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#define GPIO_IEM 0x58 /* RW - Input Enable Mask */
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#define GPIO_OES 0x70 /* WO - Output Enable Register Set */
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#define GPIO_OEC 0x74 /* WO - Output Enable Register Clear */
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struct npcm_gpio_priv {
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void __iomem *base;
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};
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static int npcm_gpio_direction_input(struct udevice *dev, unsigned int offset)
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{
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struct npcm_gpio_priv *priv = dev_get_priv(dev);
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writel(BIT(offset), priv->base + GPIO_OEC);
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setbits_le32(priv->base + GPIO_IEM, BIT(offset));
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return 0;
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}
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static int npcm_gpio_direction_output(struct udevice *dev, unsigned int offset,
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int value)
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{
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struct npcm_gpio_priv *priv = dev_get_priv(dev);
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if (value)
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setbits_le32(priv->base + GPIO_DOUT, BIT(offset));
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else
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clrbits_le32(priv->base + GPIO_DOUT, BIT(offset));
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clrbits_le32(priv->base + GPIO_IEM, BIT(offset));
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writel(BIT(offset), priv->base + GPIO_OES);
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return 0;
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}
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static int npcm_gpio_get_value(struct udevice *dev, unsigned int offset)
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{
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struct npcm_gpio_priv *priv = dev_get_priv(dev);
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if (readl(priv->base + GPIO_IEM) & BIT(offset))
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return !!(readl(priv->base + GPIO_DIN) & BIT(offset));
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if (readl(priv->base + GPIO_OE) & BIT(offset))
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return !!(readl(priv->base + GPIO_DOUT) & BIT(offset));
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return -EINVAL;
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}
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static int npcm_gpio_set_value(struct udevice *dev, unsigned int offset,
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int value)
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{
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struct npcm_gpio_priv *priv = dev_get_priv(dev);
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if (value)
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setbits_le32(priv->base + GPIO_DOUT, BIT(offset));
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else
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clrbits_le32(priv->base + GPIO_DOUT, BIT(offset));
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return 0;
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}
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static int npcm_gpio_get_function(struct udevice *dev, unsigned int offset)
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{
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struct npcm_gpio_priv *priv = dev_get_priv(dev);
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if (readl(priv->base + GPIO_IEM) & BIT(offset))
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return GPIOF_INPUT;
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if (readl(priv->base + GPIO_OE) & BIT(offset))
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return GPIOF_OUTPUT;
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return GPIOF_FUNC;
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}
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static const struct dm_gpio_ops npcm_gpio_ops = {
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.direction_input = npcm_gpio_direction_input,
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.direction_output = npcm_gpio_direction_output,
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.get_value = npcm_gpio_get_value,
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.set_value = npcm_gpio_set_value,
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.get_function = npcm_gpio_get_function,
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};
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static int npcm_gpio_probe(struct udevice *dev)
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{
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struct npcm_gpio_priv *priv = dev_get_priv(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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priv->base = dev_read_addr_ptr(dev);
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uc_priv->gpio_count = NPCM_GPIOS_PER_BANK;
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uc_priv->bank_name = dev->name;
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return 0;
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}
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static const struct udevice_id npcm_gpio_match[] = {
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{ .compatible = "nuvoton,npcm845-gpio" },
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{ .compatible = "nuvoton,npcm750-gpio" },
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{ }
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};
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U_BOOT_DRIVER(npcm_gpio) = {
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.name = "npcm_gpio",
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.id = UCLASS_GPIO,
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.of_match = npcm_gpio_match,
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.probe = npcm_gpio_probe,
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.priv_auto = sizeof(struct npcm_gpio_priv),
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.ops = &npcm_gpio_ops,
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};
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