mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-08-10 01:06:59 +02:00
d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
400 lines
8.9 KiB
C
400 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2009
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* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
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*
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* Copyright (C) 2011
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* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
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*/
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#include <common.h>
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#include <errno.h>
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#include <dm.h>
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#include <malloc.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <dt-structs.h>
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#include <mapmem.h>
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enum mxc_gpio_direction {
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MXC_GPIO_DIRECTION_IN,
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MXC_GPIO_DIRECTION_OUT,
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};
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#define GPIO_PER_BANK 32
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struct mxc_gpio_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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/* Put this first since driver model will copy the data here */
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struct dtd_gpio_mxc dtplat;
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#endif
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int bank_index;
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struct gpio_regs *regs;
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};
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struct mxc_bank_info {
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struct gpio_regs *regs;
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};
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#if !CONFIG_IS_ENABLED(DM_GPIO)
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#define GPIO_TO_PORT(n) ((n) / 32)
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/* GPIO port description */
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static unsigned long gpio_ports[] = {
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[0] = GPIO1_BASE_ADDR,
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[1] = GPIO2_BASE_ADDR,
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[2] = GPIO3_BASE_ADDR,
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#if defined(CONFIG_MX51) || \
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defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
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defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
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defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
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[3] = GPIO4_BASE_ADDR,
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#endif
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#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
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defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
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defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
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[4] = GPIO5_BASE_ADDR,
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#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
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defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT1050))
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[5] = GPIO6_BASE_ADDR,
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#endif
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#endif
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#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
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defined(CONFIG_ARCH_IMX8)
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#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
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[6] = GPIO7_BASE_ADDR,
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#endif
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#endif
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#if defined(CONFIG_ARCH_IMX8)
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[7] = GPIO8_BASE_ADDR,
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#endif
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};
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static int mxc_gpio_direction(unsigned int gpio,
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enum mxc_gpio_direction direction)
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{
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unsigned int port = GPIO_TO_PORT(gpio);
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struct gpio_regs *regs;
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u32 l;
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if (port >= ARRAY_SIZE(gpio_ports))
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return -1;
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gpio &= 0x1f;
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regs = (struct gpio_regs *)gpio_ports[port];
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l = readl(®s->gpio_dir);
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switch (direction) {
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case MXC_GPIO_DIRECTION_OUT:
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l |= 1 << gpio;
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break;
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case MXC_GPIO_DIRECTION_IN:
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l &= ~(1 << gpio);
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}
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writel(l, ®s->gpio_dir);
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return 0;
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}
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int gpio_set_value(unsigned gpio, int value)
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{
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unsigned int port = GPIO_TO_PORT(gpio);
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struct gpio_regs *regs;
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u32 l;
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if (port >= ARRAY_SIZE(gpio_ports))
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return -1;
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gpio &= 0x1f;
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regs = (struct gpio_regs *)gpio_ports[port];
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l = readl(®s->gpio_dr);
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if (value)
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l |= 1 << gpio;
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else
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l &= ~(1 << gpio);
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writel(l, ®s->gpio_dr);
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return 0;
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}
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int gpio_get_value(unsigned gpio)
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{
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unsigned int port = GPIO_TO_PORT(gpio);
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struct gpio_regs *regs;
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u32 val;
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if (port >= ARRAY_SIZE(gpio_ports))
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return -1;
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gpio &= 0x1f;
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regs = (struct gpio_regs *)gpio_ports[port];
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val = (readl(®s->gpio_psr) >> gpio) & 0x01;
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return val;
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}
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int gpio_request(unsigned gpio, const char *label)
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{
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unsigned int port = GPIO_TO_PORT(gpio);
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if (port >= ARRAY_SIZE(gpio_ports))
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return -1;
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return 0;
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}
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int gpio_free(unsigned gpio)
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{
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return 0;
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}
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int gpio_direction_input(unsigned gpio)
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{
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return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
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}
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int gpio_direction_output(unsigned gpio, int value)
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{
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int ret = gpio_set_value(gpio, value);
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if (ret < 0)
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return ret;
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return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
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}
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#endif
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#if CONFIG_IS_ENABLED(DM_GPIO)
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#include <fdtdec.h>
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static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
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{
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u32 val;
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val = readl(®s->gpio_dir);
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return val & (1 << offset) ? 1 : 0;
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}
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static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
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enum mxc_gpio_direction direction)
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{
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u32 l;
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l = readl(®s->gpio_dir);
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switch (direction) {
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case MXC_GPIO_DIRECTION_OUT:
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l |= 1 << offset;
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break;
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case MXC_GPIO_DIRECTION_IN:
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l &= ~(1 << offset);
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}
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writel(l, ®s->gpio_dir);
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}
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static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
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int value)
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{
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u32 l;
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l = readl(®s->gpio_dr);
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if (value)
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l |= 1 << offset;
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else
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l &= ~(1 << offset);
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writel(l, ®s->gpio_dr);
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}
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static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
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{
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return (readl(®s->gpio_psr) >> offset) & 0x01;
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}
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/* set GPIO pin 'gpio' as an input */
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static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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struct mxc_bank_info *bank = dev_get_priv(dev);
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/* Configure GPIO direction as input. */
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mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
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return 0;
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}
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/* set GPIO pin 'gpio' as an output, with polarity 'value' */
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static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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struct mxc_bank_info *bank = dev_get_priv(dev);
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/* Configure GPIO output value. */
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mxc_gpio_bank_set_value(bank->regs, offset, value);
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/* Configure GPIO direction as output. */
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mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
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return 0;
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}
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/* read GPIO IN value of pin 'gpio' */
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static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct mxc_bank_info *bank = dev_get_priv(dev);
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return mxc_gpio_bank_get_value(bank->regs, offset);
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}
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/* write GPIO OUT value to pin 'gpio' */
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static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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struct mxc_bank_info *bank = dev_get_priv(dev);
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mxc_gpio_bank_set_value(bank->regs, offset, value);
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return 0;
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}
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static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct mxc_bank_info *bank = dev_get_priv(dev);
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/* GPIOF_FUNC is not implemented yet */
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if (mxc_gpio_is_output(bank->regs, offset))
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return GPIOF_OUTPUT;
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else
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return GPIOF_INPUT;
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}
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static const struct dm_gpio_ops gpio_mxc_ops = {
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.direction_input = mxc_gpio_direction_input,
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.direction_output = mxc_gpio_direction_output,
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.get_value = mxc_gpio_get_value,
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.set_value = mxc_gpio_set_value,
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.get_function = mxc_gpio_get_function,
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};
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static int mxc_gpio_probe(struct udevice *dev)
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{
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struct mxc_bank_info *bank = dev_get_priv(dev);
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struct mxc_gpio_plat *plat = dev_get_plat(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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int banknum;
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char name[18], *str;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_gpio_mxc *dtplat = &plat->dtplat;
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plat->regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
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#endif
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banknum = plat->bank_index;
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if (IS_ENABLED(CONFIG_ARCH_IMX8))
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sprintf(name, "GPIO%d_", banknum);
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else
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sprintf(name, "GPIO%d_", banknum + 1);
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str = strdup(name);
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if (!str)
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return -ENOMEM;
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uc_priv->bank_name = str;
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uc_priv->gpio_count = GPIO_PER_BANK;
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bank->regs = plat->regs;
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return 0;
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}
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static int mxc_gpio_of_to_plat(struct udevice *dev)
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{
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struct mxc_gpio_plat *plat = dev_get_plat(dev);
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if (!CONFIG_IS_ENABLED(OF_PLATDATA)) {
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fdt_addr_t addr;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->regs = (struct gpio_regs *)addr;
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}
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plat->bank_index = dev_seq(dev);
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return 0;
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}
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static int mxc_gpio_bind(struct udevice *dev)
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{
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return 0;
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}
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static const struct udevice_id mxc_gpio_ids[] = {
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{ .compatible = "fsl,imx35-gpio" },
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{ }
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};
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U_BOOT_DRIVER(gpio_mxc) = {
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.name = "gpio_mxc",
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.id = UCLASS_GPIO,
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.ops = &gpio_mxc_ops,
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.probe = mxc_gpio_probe,
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.of_to_plat = mxc_gpio_of_to_plat,
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.plat_auto = sizeof(struct mxc_gpio_plat),
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.priv_auto = sizeof(struct mxc_bank_info),
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.of_match = mxc_gpio_ids,
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.bind = mxc_gpio_bind,
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};
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DM_DRIVER_ALIAS(gpio_mxc, fsl_imx6q_gpio)
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#if !CONFIG_IS_ENABLED(OF_CONTROL)
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static const struct mxc_gpio_plat mxc_plat[] = {
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{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
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{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
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{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
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#if defined(CONFIG_MX51) || \
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defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
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defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
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{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
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#endif
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#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
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defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
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{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
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#ifndef CONFIG_IMX8M
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{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
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#endif
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#endif
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#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
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{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
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#endif
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#if defined(CONFIG_ARCH_IMX8)
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{ 7, (struct gpio_regs *)GPIO8_BASE_ADDR },
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#endif
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};
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U_BOOT_DRVINFOS(mxc_gpios) = {
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{ "gpio_mxc", &mxc_plat[0] },
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{ "gpio_mxc", &mxc_plat[1] },
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{ "gpio_mxc", &mxc_plat[2] },
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#if defined(CONFIG_MX51) || \
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defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
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defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
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{ "gpio_mxc", &mxc_plat[3] },
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#endif
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#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
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defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
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{ "gpio_mxc", &mxc_plat[4] },
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#ifndef CONFIG_IMX8M
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{ "gpio_mxc", &mxc_plat[5] },
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#endif
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#endif
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#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
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{ "gpio_mxc", &mxc_plat[6] },
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#endif
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#if defined(CONFIG_ARCH_IMX8)
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{ "gpio_mxc", &mxc_plat[7] },
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#endif
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};
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#endif
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#endif
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