mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-08-14 11:16:58 +02:00
d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
148 lines
4.3 KiB
C
148 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Clock drivers for Qualcomm IPQ40xx
|
|
*
|
|
* Copyright (c) 2020 Sartura Ltd.
|
|
*
|
|
* Author: Robert Marko <robert.marko@sartura.hr>
|
|
*
|
|
*/
|
|
|
|
#include <clk-uclass.h>
|
|
#include <common.h>
|
|
#include <dm.h>
|
|
#include <errno.h>
|
|
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
|
|
|
|
#include "clock-qcom.h"
|
|
|
|
static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
switch (clk->id) {
|
|
case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
|
|
/* This clock is already initialized by SBL1 */
|
|
return 1843200;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int ipq4019_clk_enable(struct clk *clk)
|
|
{
|
|
switch (clk->id) {
|
|
case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
|
|
/* This clock is already initialized by SBL1 */
|
|
return 0;
|
|
case GCC_PRNG_AHB_CLK: /*PRNG*/
|
|
/* This clock is already initialized by SBL1 */
|
|
return 0;
|
|
case GCC_USB3_MASTER_CLK:
|
|
case GCC_USB3_SLEEP_CLK:
|
|
case GCC_USB3_MOCK_UTMI_CLK:
|
|
case GCC_USB2_MASTER_CLK:
|
|
case GCC_USB2_SLEEP_CLK:
|
|
case GCC_USB2_MOCK_UTMI_CLK:
|
|
/* These clocks is already initialized by SBL1 */
|
|
return 0;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static const struct qcom_reset_map gcc_ipq4019_resets[] = {
|
|
[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
|
|
[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
|
|
[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
|
|
[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
|
|
[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
|
|
[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
|
|
[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
|
|
[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
|
|
[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
|
|
[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
|
|
[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
|
|
[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
|
|
[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
|
|
[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
|
|
[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
|
|
[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
|
|
[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
|
|
[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
|
|
[PCIE_AHB_ARES] = { 0x1d010, 10 },
|
|
[PCIE_PWR_ARES] = { 0x1d010, 9 },
|
|
[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
|
|
[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
|
|
[PCIE_PHY_ARES] = { 0x1d010, 6 },
|
|
[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
|
|
[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
|
|
[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
|
|
[PCIE_PIPE_ARES] = { 0x1d010, 2 },
|
|
[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
|
|
[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
|
|
[ESS_RESET] = { 0x12008, 0},
|
|
[GCC_BLSP1_BCR] = {0x01000, 0},
|
|
[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
|
|
[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
|
|
[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
|
|
[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
|
|
[GCC_BIMC_BCR] = {0x04000, 0},
|
|
[GCC_TLMM_BCR] = {0x05000, 0},
|
|
[GCC_IMEM_BCR] = {0x0E000, 0},
|
|
[GCC_ESS_BCR] = {0x12008, 0},
|
|
[GCC_PRNG_BCR] = {0x13000, 0},
|
|
[GCC_BOOT_ROM_BCR] = {0x13008, 0},
|
|
[GCC_CRYPTO_BCR] = {0x16000, 0},
|
|
[GCC_SDCC1_BCR] = {0x18000, 0},
|
|
[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
|
|
[GCC_AUDIO_BCR] = {0x1B008, 0},
|
|
[GCC_QPIC_BCR] = {0x1C000, 0},
|
|
[GCC_PCIE_BCR] = {0x1D000, 0},
|
|
[GCC_USB2_BCR] = {0x1E008, 0},
|
|
[GCC_USB2_PHY_BCR] = {0x1E018, 0},
|
|
[GCC_USB3_BCR] = {0x1E024, 0},
|
|
[GCC_USB3_PHY_BCR] = {0x1E034, 0},
|
|
[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
|
|
[GCC_PCNOC_BCR] = {0x2102C, 0},
|
|
[GCC_DCD_BCR] = {0x21038, 0},
|
|
[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
|
|
[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
|
|
[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
|
|
[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
|
|
[GCC_TCSR_BCR] = {0x22000, 0},
|
|
[GCC_MPM_BCR] = {0x24000, 0},
|
|
[GCC_SPDM_BCR] = {0x25000, 0},
|
|
};
|
|
|
|
static struct msm_clk_data ipq4019_clk_data = {
|
|
.enable = ipq4019_clk_enable,
|
|
.set_rate = ipq4019_clk_set_rate,
|
|
.resets = gcc_ipq4019_resets,
|
|
.num_resets = ARRAY_SIZE(gcc_ipq4019_resets),
|
|
};
|
|
|
|
static const struct udevice_id gcc_ipq4019_of_match[] = {
|
|
{
|
|
.compatible = "qcom,gcc-ipq4019",
|
|
.data = (ulong)&ipq4019_clk_data,
|
|
},
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(gcc_ipq4019) = {
|
|
.name = "gcc_ipq4019",
|
|
.id = UCLASS_NOP,
|
|
.of_match = gcc_ipq4019_of_match,
|
|
.bind = qcom_cc_bind,
|
|
.flags = DM_FLAG_PRE_RELOC,
|
|
};
|