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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
115 lines
2.4 KiB
C
115 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Copyright 2012 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <clk-uclass.h>
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#include <dm/device.h>
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#include <dm/devres.h>
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#include <linux/clk-provider.h>
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#include <div64.h>
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#include <clk.h>
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#include "clk.h"
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#include <linux/err.h>
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#define UBOOT_DM_CLK_IMX_PFD "imx_clk_pfd"
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struct clk_pfd {
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struct clk clk;
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void __iomem *reg;
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u8 idx;
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};
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#define to_clk_pfd(_clk) container_of(_clk, struct clk_pfd, clk)
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#define SET 0x4
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#define CLR 0x8
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#define OTG 0xc
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static unsigned long clk_pfd_recalc_rate(struct clk *clk)
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{
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struct clk_pfd *pfd =
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to_clk_pfd(dev_get_clk_ptr(clk->dev));
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unsigned long parent_rate = clk_get_parent_rate(clk);
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u64 tmp = parent_rate;
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u8 frac = (readl(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
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tmp *= 18;
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do_div(tmp, frac);
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return tmp;
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}
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static unsigned long clk_pfd_set_rate(struct clk *clk, unsigned long rate)
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{
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struct clk_pfd *pfd = to_clk_pfd(clk);
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unsigned long parent_rate = clk_get_parent_rate(clk);
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u64 tmp = parent_rate;
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u8 frac;
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tmp = tmp * 18 + rate / 2;
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do_div(tmp, rate);
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frac = tmp;
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if (frac < 12)
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frac = 12;
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else if (frac > 35)
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frac = 35;
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writel(0x3f << (pfd->idx * 8), pfd->reg + CLR);
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writel(frac << (pfd->idx * 8), pfd->reg + SET);
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return 0;
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}
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static const struct clk_ops clk_pfd_ops = {
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.get_rate = clk_pfd_recalc_rate,
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.set_rate = clk_pfd_set_rate,
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};
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struct clk *imx_clk_pfd(const char *name, const char *parent_name,
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void __iomem *reg, u8 idx)
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{
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struct clk_pfd *pfd;
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struct clk *clk;
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int ret;
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pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
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if (!pfd)
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return ERR_PTR(-ENOMEM);
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pfd->reg = reg;
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pfd->idx = idx;
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/* register the clock */
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clk = &pfd->clk;
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ret = clk_register(clk, UBOOT_DM_CLK_IMX_PFD, name, parent_name);
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if (ret) {
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kfree(pfd);
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return ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(clk_pfd) = {
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.name = UBOOT_DM_CLK_IMX_PFD,
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.id = UCLASS_CLK,
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.ops = &clk_pfd_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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