mirror of
https://source.denx.de/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
424 lines
10 KiB
C
424 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
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* Copyright (C) Jasbir Matharu
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* Copyright (C) UDOO Team
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*
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* Author: Breno Lima <breno.lima@nxp.com>
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* Author: Francesco Montefoschi <francesco.monte@gmail.com>
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*/
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#include <init.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/sections.h>
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#include <dm.h>
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#include <env.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/arch/sys_proto.h>
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#include <spl.h>
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#include <linux/delay.h>
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#include <linux/sizes.h>
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#include <common.h>
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#include <i2c.h>
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include <malloc.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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UDOO_NEO_TYPE_BASIC,
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UDOO_NEO_TYPE_BASIC_KS,
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UDOO_NEO_TYPE_FULL,
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UDOO_NEO_TYPE_EXTENDED,
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};
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
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#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
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#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm)
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#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
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#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \
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MUX_MODE_SION)
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#define OCRAM_START 0x8f8000
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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int power_init_board(void)
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{
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struct udevice *dev;
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int ret, dev_id, rev_id;
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ret = pmic_get("pfuze3000@8", &dev);
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if (ret == -ENODEV)
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return 0;
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if (ret != 0)
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return ret;
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dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
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rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
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printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
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pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
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return 0;
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}
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/* CD pin */
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MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* Power */
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MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const phy_control_pads[] = {
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/* 25MHz Ethernet PHY Clock */
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MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
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MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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};
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static iomux_v3_cfg_t const wdog_b_pad = {
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MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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static iomux_v3_cfg_t const peri_3v3_pads[] = {
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MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static int setup_fec(void)
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{
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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int reg;
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imx_iomux_v3_setup_multiple_pads(phy_control_pads,
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ARRAY_SIZE(phy_control_pads));
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/* Reset PHY */
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gpio_request(IMX_GPIO_NR(2, 1), "enet_rst");
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gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
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udelay(10000);
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gpio_set_value(IMX_GPIO_NR(2, 1), 1);
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udelay(100);
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reg = readl(&anatop->pll_enet);
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reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
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writel(reg, &anatop->pll_enet);
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return enable_fec_anatop_clock(0, ENET_25MHZ);
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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/*
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* Because kernel set WDOG_B mux before pad with the commone pinctrl
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* framwork now and wdog reset will be triggered once set WDOG_B mux
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* with default pad setting, we set pad setting here to workaround this.
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* Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
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* as GPIO mux firstly here to workaround it.
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*/
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imx_iomux_v3_setup_pad(wdog_b_pad);
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/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
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imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
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ARRAY_SIZE(peri_3v3_pads));
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/* Active high for ncp692 */
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gpio_request(IMX_GPIO_NR(4, 16), "ncp692");
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gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
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setup_fec();
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return 0;
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}
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static struct fsl_esdhc_cfg usdhc_cfg[1] = {
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{USDHC2_BASE_ADDR},
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};
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#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
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#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2)
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int board_mmc_getcd(struct mmc *mmc)
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{
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return !gpio_get_value(USDHC2_CD_GPIO);
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}
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int board_mmc_init(struct bd_info *bis)
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{
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SETUP_IOMUX_PADS(usdhc2_pads);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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usdhc_cfg[0].max_bus_width = 4;
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gpio_request(IMX_GPIO_NR(6, 1), "usdhc2_pwr");
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gpio_request(IMX_GPIO_NR(6, 2), "usdhc2_cd");
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gpio_direction_input(USDHC2_CD_GPIO);
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gpio_direction_output(USDHC2_PWR_GPIO, 1);
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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}
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static char *board_string(int type)
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{
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switch (type) {
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case UDOO_NEO_TYPE_BASIC:
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return "BASIC";
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case UDOO_NEO_TYPE_BASIC_KS:
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return "BASICKS";
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case UDOO_NEO_TYPE_FULL:
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return "FULL";
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case UDOO_NEO_TYPE_EXTENDED:
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return "EXTENDED";
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}
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return "UNDEFINED";
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}
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/* Override the default implementation, DT model is not accurate */
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int checkboard(void)
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{
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int *board_type = (int *)OCRAM_START;
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printf("Board: UDOO Neo %s\n", board_string(*board_type));
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return 0;
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}
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int board_late_init(void)
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{
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int *board_type = (int *)OCRAM_START;
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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env_set("board_name", board_string(*board_type));
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#endif
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#include <linux/libfdt.h>
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#include <asm/arch/mx6-ddr.h>
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static const iomux_v3_cfg_t board_recognition_pads[] = {
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/*Connected to R184*/
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MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
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/*Connected to R185*/
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MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
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};
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static int get_board_value(void)
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{
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int r184, r185;
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imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
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ARRAY_SIZE(board_recognition_pads));
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gpio_request(IMX_GPIO_NR(4, 13), "r184");
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gpio_request(IMX_GPIO_NR(4, 0), "r185");
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gpio_direction_input(IMX_GPIO_NR(4, 13));
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gpio_direction_input(IMX_GPIO_NR(4, 0));
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r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
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r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
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/*
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* Machine selection -
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* Machine r184, r185
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* ---------------------------------
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* Basic 0 0
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* Basic Ks 0 1
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* Full 1 0
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* Extended 1 1
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*/
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return (r184 << 1) + r185;
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}
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static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_dqm0 = 0x00000028,
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.dram_dqm1 = 0x00000028,
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.dram_dqm2 = 0x00000028,
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.dram_dqm3 = 0x00000028,
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.dram_ras = 0x00000020,
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.dram_cas = 0x00000020,
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.dram_odt0 = 0x00000020,
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.dram_odt1 = 0x00000020,
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.dram_sdba2 = 0x00000000,
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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.dram_sdclk_0 = 0x00000030,
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.dram_sdqs0 = 0x00000028,
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.dram_sdqs1 = 0x00000028,
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.dram_sdqs2 = 0x00000028,
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.dram_sdqs3 = 0x00000028,
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.dram_reset = 0x00000020,
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};
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static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
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.grp_addds = 0x00000020,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000028,
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.grp_b1ds = 0x00000028,
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.grp_ctlds = 0x00000020,
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.grp_ddr_type = 0x000c0000,
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.grp_b2ds = 0x00000028,
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.grp_b3ds = 0x00000028,
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};
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static const struct mx6_mmdc_calibration neo_mmcd_calib = {
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.p0_mpwldectrl0 = 0x000E000B,
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.p0_mpwldectrl1 = 0x000E0010,
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.p0_mpdgctrl0 = 0x41600158,
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.p0_mpdgctrl1 = 0x01500140,
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.p0_mprddlctl = 0x3A383E3E,
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.p0_mpwrdlctl = 0x3A383C38,
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};
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static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
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.p0_mpwldectrl0 = 0x001E0022,
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.p0_mpwldectrl1 = 0x001C0019,
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.p0_mpdgctrl0 = 0x41540150,
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.p0_mpdgctrl1 = 0x01440138,
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.p0_mprddlctl = 0x403E4644,
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.p0_mpwrdlctl = 0x3C3A4038,
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};
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/* MT41K256M16 */
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static struct mx6_ddr3_cfg neo_mem_ddr = {
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.mem_speed = 1600,
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.density = 4,
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.width = 16,
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.banks = 8,
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.rowaddr = 15,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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/* MT41K128M16 */
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static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
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.mem_speed = 1600,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0xFFFFFFFF, &ccm->CCGR0);
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writel(0xFFFFFFFF, &ccm->CCGR1);
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writel(0xFFFFFFFF, &ccm->CCGR2);
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writel(0xFFFFFFFF, &ccm->CCGR3);
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writel(0xFFFFFFFF, &ccm->CCGR4);
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writel(0xFFFFFFFF, &ccm->CCGR5);
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writel(0xFFFFFFFF, &ccm->CCGR6);
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writel(0xFFFFFFFF, &ccm->CCGR7);
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}
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static void spl_dram_init(void)
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{
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int *board_type = (int *)OCRAM_START;
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struct mx6_ddr_sysinfo sysinfo = {
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.dsize = 1, /* width of data bus: 1 = 32 bits */
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.cs_density = 24,
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 2,
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.rtt_nom = 2, /* RTT_Nom = RZQ/2 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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};
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*board_type = get_board_value();
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mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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if (*board_type == UDOO_NEO_TYPE_BASIC ||
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*board_type == UDOO_NEO_TYPE_BASIC_KS)
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mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
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&neo_basic_mem_ddr);
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else
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mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
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}
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void board_init_f(ulong dummy)
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{
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ccgr_init();
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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/* setup GP timer */
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timer_init();
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/* Enable device tree and early DM support*/
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spl_early_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* DDR initialization */
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spl_dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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/* load/boot image from boot device */
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board_init_r(NULL, 0);
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}
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#endif
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