mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-08-10 09:17:00 +02:00
d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
270 lines
6.6 KiB
C
270 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Technexion Ltd.
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*
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* Author: Richard Hu <richard.hu@technexion.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx7-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch-mx7/mx7-ddr.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/gpio.h>
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#include <asm/sections.h>
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#include <fsl_esdhc_imx.h>
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#include <spl.h>
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#if defined(CONFIG_SPL_BUILD)
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* Break into full U-Boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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return 0;
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}
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#endif
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static struct ddrc ddrc_regs_val = {
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.mstr = 0x01040001,
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.rfshtmg = 0x00400046,
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.init1 = 0x00690000,
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.init0 = 0x00020083,
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.init3 = 0x09300004,
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.init4 = 0x04080000,
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.init5 = 0x00100004,
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.rankctl = 0x0000033F,
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.dramtmg0 = 0x09081109,
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.dramtmg1 = 0x0007020d,
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.dramtmg2 = 0x03040407,
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.dramtmg3 = 0x00002006,
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.dramtmg4 = 0x04020205,
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.dramtmg5 = 0x03030202,
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.dramtmg8 = 0x00000803,
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.zqctl0 = 0x00800020,
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.dfitmg0 = 0x02098204,
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.dfitmg1 = 0x00030303,
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.dfiupd0 = 0x80400003,
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.dfiupd1 = 0x00100020,
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.dfiupd2 = 0x80100004,
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.addrmap4 = 0x00000F0F,
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.odtcfg = 0x06000604,
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.odtmap = 0x00000001,
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.rfshtmg = 0x00400046,
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.dramtmg0 = 0x09081109,
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.addrmap0 = 0x0000001f,
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.addrmap1 = 0x00080808,
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.addrmap2 = 0x00000000,
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.addrmap3 = 0x00000000,
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.addrmap4 = 0x00000f0f,
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.addrmap5 = 0x07070707,
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.addrmap6 = 0x0f0f0707,
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};
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static struct ddrc_mp ddrc_mp_val = {
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.pctrl_0 = 0x00000001,
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};
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static struct ddr_phy ddr_phy_regs_val = {
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.phy_con0 = 0x17420f40,
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.phy_con1 = 0x10210100,
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.phy_con4 = 0x00060807,
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.mdll_con0 = 0x1010007e,
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.drvds_con0 = 0x00000d6e,
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.cmd_sdll_con0 = 0x00000010,
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.offset_lp_con0 = 0x0000000f,
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.offset_rd_con0 = 0x08080808,
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.offset_wr_con0 = 0x08080808,
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};
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static struct mx7_calibration calib_param = {
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.num_val = 5,
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.values = {
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0x0E407304,
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0x0E447304,
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0x0E447306,
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0x0E447304,
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0x0E447304,
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},
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};
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static void gpr_init(void)
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{
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struct iomuxc_gpr_base_regs *gpr_regs =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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writel(0x4F400005, &gpr_regs->gpr[1]);
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}
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/*
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* Revision Detection
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*
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* GPIO1_12 GPIO1_13
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* 0 0 1GB DDR3
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* 0 1 2GB DDR3
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* 1 0 512MB DDR3
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*/
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static int imx7d_pico_detect_board(void)
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{
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gpio_direction_input(IMX_GPIO_NR(1, 12));
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gpio_direction_input(IMX_GPIO_NR(1, 13));
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return gpio_get_value(IMX_GPIO_NR(1, 12)) << 1 |
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gpio_get_value(IMX_GPIO_NR(1, 13));
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}
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static void ddr_init(void)
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{
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switch (imx7d_pico_detect_board()) {
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case 0:
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ddrc_regs_val.addrmap6 = 0x0f070707;
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break;
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case 1:
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ddrc_regs_val.addrmap0 = 0x0000001f;
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ddrc_regs_val.addrmap1 = 0x00181818;
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ddrc_regs_val.addrmap4 = 0x00000f0f;
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ddrc_regs_val.addrmap5 = 0x04040404;
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ddrc_regs_val.addrmap6 = 0x04040404;
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break;
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}
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mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
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&calib_param);
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}
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void board_init_f(ulong dummy)
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{
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arch_cpu_init();
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gpr_init();
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board_early_init_f();
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timer_init();
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preloader_console_init();
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ddr_init();
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memset(__bss_start, 0, __bss_end - __bss_start);
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board_init_r(NULL, 0);
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}
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void reset_cpu(void)
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{
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}
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#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
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#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
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/* EMMC/SD */
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static const iomux_v3_cfg_t usdhc1_pads[] = {
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MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14)
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static const iomux_v3_cfg_t usdhc3_emmc_pads[] = {
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MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static struct fsl_esdhc_cfg usdhc_cfg[2] = {
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{USDHC3_BASE_ADDR},
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{USDHC1_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC1_BASE_ADDR:
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ret = !gpio_get_value(USDHC1_CD_GPIO);
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break;
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case USDHC3_BASE_ADDR:
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ret = !gpio_get_value(USDHC3_CD_GPIO);
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break;
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}
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return ret;
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}
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int board_mmc_init(struct bd_info *bis)
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{
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int ret;
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u32 index;
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/*
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* Following map is done:
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* (USDHC) (Physical Port)
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* usdhc3 SOM MicroSD/MMC
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* usdhc1 Carrier board MicroSD
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* Always set boot USDHC as mmc0
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*/
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imx_iomux_v3_setup_multiple_pads(usdhc3_emmc_pads,
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ARRAY_SIZE(usdhc3_emmc_pads));
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gpio_direction_input(USDHC3_CD_GPIO);
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imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
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ARRAY_SIZE(usdhc1_pads));
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gpio_direction_input(USDHC1_CD_GPIO);
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switch (get_boot_device()) {
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case SD1_BOOT:
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usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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usdhc_cfg[0].max_bus_width = 4;
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usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[1].max_bus_width = 4;
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break;
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case MMC3_BOOT:
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usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[0].max_bus_width = 8;
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usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR;
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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usdhc_cfg[1].max_bus_width = 4;
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break;
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case SD3_BOOT:
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default:
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usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[0].max_bus_width = 4;
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usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR;
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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usdhc_cfg[1].max_bus_width = 4;
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break;
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}
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for (index = 0; index < CFG_SYS_FSL_USDHC_NUM; ++index) {
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif
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