mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-08-10 17:26:59 +02:00
d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
368 lines
10 KiB
C
368 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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* Copyright (C) 2014 O.S. Systems Software LTDA.
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*
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* Author: Fabio Estevam <festevam@gmail.com>
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*/
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#include <common.h>
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#include <env.h>
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#include <init.h>
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#include <net.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/mach-imx/video.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include <linux/sizes.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <phy.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define ETH_PHY_RESET IMX_GPIO_NR(1, 26)
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#define LVDS0_EN IMX_GPIO_NR(2, 8)
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#define LVDS0_BL_EN IMX_GPIO_NR(2, 9)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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static void setup_iomux_uart(void)
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{
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SETUP_IOMUX_PADS(uart1_pads);
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}
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static iomux_v3_cfg_t const lvds_pads[] = {
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/* lvds */
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IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const enet_pads[] = {
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IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
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MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
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MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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/* AR8035 PHY Reset */
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IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static void setup_iomux_enet(void)
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{
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SETUP_IOMUX_PADS(enet_pads);
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/* Reset AR8031 PHY */
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gpio_request(ETH_PHY_RESET, "enet_phy_reset");
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gpio_direction_output(ETH_PHY_RESET, 0);
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udelay(500);
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gpio_set_value(ETH_PHY_RESET, 1);
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}
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#if defined(CONFIG_VIDEO_IPUV3)
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static iomux_v3_cfg_t const ft5x06_wvga_pads[] = {
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IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
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IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
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IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
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IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
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IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
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IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
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IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
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IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
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IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
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IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
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IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
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IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
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IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
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IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
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IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
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IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
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IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
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IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
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IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
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IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
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IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
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IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
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IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
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IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18),
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IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19),
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IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20),
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IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21),
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IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22),
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IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23),
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IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
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IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
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};
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static void do_enable_hdmi(struct display_info_t const *dev)
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{
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imx_enable_hdmi_phy();
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}
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static void enable_lvds(struct display_info_t const *dev)
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{
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struct iomuxc *iomux = (struct iomuxc *)
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IOMUXC_BASE_ADDR;
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/* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
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u32 reg = readl(&iomux->gpr[2]);
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reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
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writel(reg, &iomux->gpr[2]);
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/* Enable Backlight - use GPIO for Brightness adjustment */
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SETUP_IOMUX_PAD(PAD_SD4_DAT1__GPIO2_IO09);
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gpio_request(IMX_GPIO_NR(2, 9), "backlight_enable");
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gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
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gpio_request(IMX_GPIO_NR(2, 8), "brightness");
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SETUP_IOMUX_PAD(PAD_SD4_DAT0__GPIO2_IO08);
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gpio_direction_output(IMX_GPIO_NR(2, 8), 1);
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}
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static void enable_ft5x06_wvga(struct display_info_t const *dev)
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{
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SETUP_IOMUX_PADS(ft5x06_wvga_pads);
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gpio_request(IMX_GPIO_NR(2, 10), "parallel_enable");
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gpio_request(IMX_GPIO_NR(2, 11), "parallel_brightness");
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gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
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gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
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}
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struct display_info_t const displays[] = {{
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.bus = 1,
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.addr = 0x38,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = NULL,
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.enable = enable_ft5x06_wvga,
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.mode = {
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.name = "FT5x06-WVGA",
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.refresh = 60,
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.xres = 800,
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.yres = 480,
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.pixclock = 30303,
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.left_margin = 45,
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.right_margin = 210,
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.upper_margin = 22,
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.lower_margin = 22,
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.hsync_len = 1,
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.vsync_len = 1,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED
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} }, {
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = NULL,
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.enable = enable_lvds,
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.mode = {
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.name = "hj070na",
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.refresh = 60,
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.xres = 1024,
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.yres = 600,
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.pixclock = 15385,
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.left_margin = 220,
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.right_margin = 40,
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.upper_margin = 21,
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.lower_margin = 7,
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.hsync_len = 60,
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.vsync_len = 10,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} }, {
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_hdmi,
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.enable = do_enable_hdmi,
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.mode = {
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.name = "HDMI",
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15385,
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.left_margin = 220,
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.right_margin = 40,
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.upper_margin = 21,
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.lower_margin = 7,
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.hsync_len = 60,
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.vsync_len = 10,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} } };
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size_t display_count = ARRAY_SIZE(displays);
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static void setup_display(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int reg;
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/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
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SETUP_IOMUX_PADS(lvds_pads);
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gpio_request(LVDS0_EN, "lvds0_enable");
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gpio_request(LVDS0_BL_EN, "lvds0_bl_enable");
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gpio_direction_output(LVDS0_EN, 1);
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gpio_direction_output(LVDS0_BL_EN, 1);
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enable_ipu_clock();
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imx_setup_hdmi();
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reg = __raw_readl(&mxc_ccm->CCGR3);
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reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
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writel(reg, &mxc_ccm->CCGR3);
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/* set LDB0, LDB1 clk select to 011/011 */
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reg = readl(&mxc_ccm->cs2cdr);
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reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
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| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
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reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
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| (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->cs2cdr);
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reg = readl(&mxc_ccm->cscmr2);
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reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
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writel(reg, &mxc_ccm->cscmr2);
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reg = readl(&mxc_ccm->chsccdr);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0
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<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0
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<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->chsccdr);
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reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
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| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
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| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
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| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
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| IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
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| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
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| IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
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| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
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| IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
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writel(reg, &iomux->gpr[2]);
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reg = readl(&iomux->gpr[3]);
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reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
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| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
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| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
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<< IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
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writel(reg, &iomux->gpr[3]);
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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#if defined(CONFIG_VIDEO_IPUV3)
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setup_display();
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#endif
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return 0;
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}
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int board_eth_init(struct bd_info *bis)
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{
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setup_iomux_enet();
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return cpu_eth_init(bis);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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unsigned short val;
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/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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val &= 0xffe7;
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val |= 0x18;
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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/* introduce tx clock delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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val |= 0x0100;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int overwrite_console(void)
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{
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return 1;
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}
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int board_late_init(void)
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{
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if (is_mx6dq())
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env_set("board_rev", "MX6Q");
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else
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env_set("board_rev", "MX6DL");
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: PICO-IMX6\n");
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return 0;
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}
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