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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
150 lines
3.7 KiB
C
150 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <log.h>
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#include <asm/io.h>
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#include "ics307_clk.h"
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#if defined(CONFIG_FSL_NGPIXIS)
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#include "ngpixis.h"
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#define fpga_reg pixis
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#elif defined(CONFIG_FSL_QIXIS)
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#include "qixis.h"
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#define fpga_reg ((struct qixis *)QIXIS_BASE)
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#else
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#include "pixis.h"
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#define fpga_reg pixis
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#endif
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/* define for SYS CLK or CLK1Frequency */
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#define TTL 1
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#define CLK2 0
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#define CRYSTAL 0
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#define MAX_VDW (511 + 8)
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#define MAX_RDW (127 + 2)
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#define MIN_VDW (4 + 8)
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#define MIN_RDW (1 + 2)
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#define NUM_OD_SETTING 8
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/*
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* These defines cover the industrial temperature range part,
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* for commercial, change below to 400000 and 55000, respectively
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*/
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#define MAX_VCO 360000
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#define MIN_VCO 60000
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/* decode S[0-2] to Output Divider (OD) */
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static u8 ics307_s_to_od[] = {
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10, 2, 8, 4, 5, 7, 3, 6
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};
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/*
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* Find one solution to generate required frequency for SYSCLK
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* out_freq: KHz, required frequency to the SYSCLK
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* the result will be retuned with component RDW, VDW, OD, TTL,
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* CLK2 and crystal
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*/
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unsigned long ics307_sysclk_calculator(unsigned long out_freq)
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{
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const unsigned long input_freq = CFG_ICS307_REFCLK_HZ;
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unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
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unsigned long tmp_out, diff, result = 0;
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int found = 0;
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for (odp = 0; odp < NUM_OD_SETTING; odp++) {
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od = ics307_s_to_od[odp];
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if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
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continue;
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for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) {
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/* Calculate the VDW */
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vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
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if (vdw > MAX_VDW)
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vdw = MAX_VDW;
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if (vdw < MIN_VDW)
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continue;
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/* Calculate the temp out frequency */
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tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
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diff = max(out_freq, tmp_out) - min(out_freq, tmp_out);
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/*
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* calculate the percent, the precision is 1/1000
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* If greater than 1/1000, continue
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* otherwise, we think the solution is we required
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*/
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if (diff * 1000 / out_freq > 1)
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continue;
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else {
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s_vdw = vdw;
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s_rdw = rdw;
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s_odp = odp;
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found = 1;
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break;
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}
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}
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}
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if (found)
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result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 |
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CLK2 << 19 | TTL << 21 | CRYSTAL << 22;
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debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,
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ics307_s_to_od[s_odp]);
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return result;
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}
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/*
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* Calculate frequency being generated by ICS307-02 clock chip based upon
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* the control bytes being programmed into it.
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*/
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static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
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{
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const unsigned long input_freq = CFG_ICS307_REFCLK_HZ;
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unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
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unsigned long rdw = cw2 & 0x7F;
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unsigned long od = ics307_s_to_od[cw0 & 0x7];
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unsigned long freq;
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/*
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* CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
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*
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* cw0: C1 C0 TTL F1 F0 S2 S1 S0
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* cw1: V8 V7 V6 V5 V4 V3 V2 V1
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* cw2: V0 R6 R5 R4 R3 R2 R1 R0
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*
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* R6:R0 = Reference Divider Word (RDW)
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* V8:V0 = VCO Divider Word (VDW)
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* S2:S0 = Output Divider Select (OD)
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* F1:F0 = Function of CLK2 Output
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* TTL = duty cycle
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* C1:C0 = internal load capacitance for cyrstal
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*
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*/
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freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
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debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
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freq);
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return freq;
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}
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unsigned long get_board_sys_clk(void)
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{
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return ics307_clk_freq(
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in_8(&fpga_reg->sclk[0]),
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in_8(&fpga_reg->sclk[1]),
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in_8(&fpga_reg->sclk[2]));
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}
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#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
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unsigned long get_board_ddr_clk(void)
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{
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return ics307_clk_freq(
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in_8(&fpga_reg->dclk[0]),
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in_8(&fpga_reg->dclk[1]),
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in_8(&fpga_reg->dclk[2]));
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}
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#endif
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