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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
116 lines
2.9 KiB
C
116 lines
2.9 KiB
C
// SPDX-License-Identifier: Intel
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/*
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* Copyright (C) 2015-2016 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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* Mostly taken from coreboot fsp2_0/memory_init.c
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*/
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#include <common.h>
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#include <binman.h>
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#include <bootstage.h>
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#include <dm.h>
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#include <log.h>
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#include <asm/global_data.h>
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#include <asm/mrccache.h>
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#include <asm/fsp/fsp_infoheader.h>
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#include <asm/fsp2/fsp_api.h>
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#include <asm/fsp2/fsp_internal.h>
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#include <asm/arch/fsp/fsp_configs.h>
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#include <asm/arch/fsp/fsp_m_upd.h>
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static int prepare_mrc_cache_type(enum mrc_type_t type,
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struct mrc_data_container **cachep)
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{
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struct mrc_data_container *cache;
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struct mrc_region entry;
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int ret;
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ret = mrccache_get_region(type, NULL, &entry);
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if (ret)
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return ret;
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cache = mrccache_find_current(&entry);
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if (!cache)
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return -ENOENT;
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log_debug("MRC at %x, size %x\n", (uint)cache->data, cache->data_size);
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*cachep = cache;
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return 0;
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}
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int prepare_mrc_cache(struct fspm_upd *upd)
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{
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struct mrc_data_container *cache;
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int ret;
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ret = prepare_mrc_cache_type(MRC_TYPE_NORMAL, &cache);
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if (ret)
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return log_msg_ret("Cannot get normal cache", ret);
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upd->arch.nvs_buffer_ptr = cache->data;
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ret = prepare_mrc_cache_type(MRC_TYPE_VAR, &cache);
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if (ret)
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return log_msg_ret("Cannot get var cache", ret);
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upd->config.variable_nvs_buffer_ptr = cache->data;
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return 0;
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}
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int fsp_memory_init(bool s3wake, bool use_spi_flash)
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{
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struct fspm_upd upd, *fsp_upd;
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fsp_memory_init_func func;
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struct binman_entry entry;
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struct fsp_header *hdr;
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struct hob_header *hob;
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struct udevice *dev;
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int delay;
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int ret;
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log_debug("Locating FSP\n");
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ret = fsp_locate_fsp(FSP_M, &entry, use_spi_flash, &dev, &hdr, NULL);
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if (ret)
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return log_msg_ret("locate FSP", ret);
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debug("Found FSP_M at %x, size %x\n", hdr->img_base, hdr->img_size);
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/* Copy over the default config */
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fsp_upd = (struct fspm_upd *)(hdr->img_base + hdr->cfg_region_off);
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if (fsp_upd->header.signature != FSPM_UPD_SIGNATURE)
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return log_msg_ret("Bad UPD signature", -EPERM);
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memcpy(&upd, fsp_upd, sizeof(upd));
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delay = dev_read_u32_default(dev, "fspm,training-delay", 0);
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ret = fspm_update_config(dev, &upd);
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if (ret) {
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if (ret != -ENOENT)
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return log_msg_ret("Could not setup config", ret);
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} else {
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delay = 0;
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}
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if (delay)
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printf("SDRAM training (%d seconds)...", delay);
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else
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log_debug("SDRAM init...");
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bootstage_start(BOOTSTAGE_ID_ACCUM_FSP_M, "fsp-m");
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func = (fsp_memory_init_func)(hdr->img_base + hdr->fsp_mem_init);
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ret = func(&upd, &hob);
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bootstage_accum(BOOTSTAGE_ID_ACCUM_FSP_M);
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cpu_reinit_fpu();
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if (delay)
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printf("done\n");
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else
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log_debug("done\n");
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if (ret)
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return log_msg_ret("SDRAM init fail\n", ret);
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gd->arch.hob_list = hob;
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ret = fspm_done(dev);
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if (ret)
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return log_msg_ret("fsm_done\n", ret);
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return 0;
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}
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