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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
138 lines
3.4 KiB
C
138 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* clk-synthesizer.c
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*
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* Clock synthesizer apis
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*
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* Copyright (C) 2016, Texas Instruments, Incorporated - https://www.ti.com/
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*/
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#include <common.h>
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#include <asm/arch/clk_synthesizer.h>
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#include <i2c.h>
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/**
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* clk_synthesizer_reg_read - Read register from synthesizer.
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* dev: i2c bus device (not used if CONFIG_DM_I2C is not set)
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* @addr: addr within the i2c device
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* buf: Buffer to which value is to be read.
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*
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* For reading the register from this clock synthesizer, a command needs to
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* be send along with enabling byte read more, and then read can happen.
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* Returns 0 on success
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*/
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static int clk_synthesizer_reg_read(struct udevice *dev, int addr, u8 *buf)
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{
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int rc;
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/* Enable Bye read */
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addr = addr | CLK_SYNTHESIZER_BYTE_MODE;
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#if !CONFIG_IS_ENABLED(DM_I2C)
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/* Send the command byte */
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rc = i2c_write(CONFIG_CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1);
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if (rc)
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printf("Failed to send command to clock synthesizer\n");
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/* Read the Data */
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return i2c_read(CONFIG_CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1);
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#else
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/* Send the command byte */
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rc = dm_i2c_reg_write(dev, addr, *buf);
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if (rc)
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printf("Failed to send command to clock synthesizer\n");
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/* Read the Data */
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rc = dm_i2c_reg_read(dev, addr);
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if (rc < 0)
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return rc;
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*buf = (u8)rc;
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return 0;
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#endif
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}
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/**
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* clk_synthesizer_reg_write - Write a value to register in synthesizer.
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* dev: i2c bus device (not used if CONFIG_DM_I2C is not set)
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* @addr: addr within the i2c device
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* val: Value to be written in the addr.
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*
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* Enable the byte read mode in the address and start the i2c transfer.
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* Returns 0 on success
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*/
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static int clk_synthesizer_reg_write(struct udevice *dev, int addr, u8 val)
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{
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u8 cmd[2];
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int rc = 0;
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/* Enable byte write */
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cmd[0] = addr | CLK_SYNTHESIZER_BYTE_MODE;
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cmd[1] = val;
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#if !CONFIG_IS_ENABLED(DM_I2C)
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rc = i2c_write(CONFIG_CLK_SYNTHESIZER_I2C_ADDR, addr, 1, cmd, 2);
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#else
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rc = dm_i2c_write(dev, addr, cmd, 2);
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#endif
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if (rc)
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printf("Clock synthesizer reg write failed at addr = 0x%x\n",
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addr);
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return rc;
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}
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/**
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* setup_clock_syntherizer - Program the clock synthesizer to get the desired
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* frequency.
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* @data: Data containing the desired output
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*
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* This is a PLL-based high performance synthesizer which gives 3 outputs
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* as per the PLL_DIV and load capacitor programmed.
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*/
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int setup_clock_synthesizer(struct clk_synth *data)
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{
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int rc;
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u8 val = 0;
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struct udevice *dev = NULL;
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#if !CONFIG_IS_ENABLED(DM_I2C)
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rc = i2c_probe(CONFIG_CLK_SYNTHESIZER_I2C_ADDR);
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if (rc) {
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printf("i2c probe failed at address 0x%x\n",
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CONFIG_CLK_SYNTHESIZER_I2C_ADDR);
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return rc;
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}
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#else
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rc = i2c_get_chip_for_busnum(0, CONFIG_CLK_SYNTHESIZER_I2C_ADDR, 1, &dev);
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if (rc) {
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printf("failed to get device for synthesizer at address 0x%x\n",
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CONFIG_CLK_SYNTHESIZER_I2C_ADDR);
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return rc;
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}
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#endif
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rc = clk_synthesizer_reg_read(dev, CLK_SYNTHESIZER_ID_REG, &val);
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if (val != data->id)
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return rc;
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/* Crystal Load capacitor selection */
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rc = clk_synthesizer_reg_write(dev, CLK_SYNTHESIZER_XCSEL,
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data->capacitor);
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if (rc)
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return rc;
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rc = clk_synthesizer_reg_write(dev, CLK_SYNTHESIZER_MUX_REG,
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data->mux);
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if (rc)
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return rc;
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rc = clk_synthesizer_reg_write(dev, CLK_SYNTHESIZER_PDIV2_REG,
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data->pdiv2);
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if (rc)
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return rc;
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rc = clk_synthesizer_reg_write(dev, CLK_SYNTHESIZER_PDIV3_REG,
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data->pdiv3);
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if (rc)
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return rc;
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return 0;
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}
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