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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
75 lines
2.4 KiB
C
75 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* LPC32xx dram init
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*
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* (C) Copyright 2014 DENX Software Engineering GmbH
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* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
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*
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* This is called by SPL to gain access to the SDR DRAM.
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*
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* This code runs from SRAM.
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/wdt.h>
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#include <asm/arch/emc.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
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static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
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void ddr_init(struct emc_dram_settings *dram)
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{
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uint32_t ck;
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/* Enable EMC interface and choose little endian mode */
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writel(1, &emc->ctrl);
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writel(0, &emc->config);
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/* Select maximum EMC Dynamic Memory Refresh Time */
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writel(0x7FF, &emc->refresh);
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/* Determine CLK */
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ck = get_sdram_clk_rate();
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/* Configure SDRAM */
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writel(dram->cmddelay, &clk->sdramclk_ctrl);
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writel(dram->config0, &emc->config0);
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writel(dram->rascas0, &emc->rascas0);
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writel(dram->rdconfig, &emc->read_config);
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/* Set timings */
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writel((ck / dram->trp) & 0x0000000F, &emc->t_rp);
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writel((ck / dram->tras) & 0x0000000F, &emc->t_ras);
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writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex);
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writel((ck / dram->twr) & 0x0000000F, &emc->t_wr);
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writel((ck / dram->trc) & 0x0000001F, &emc->t_rc);
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writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc);
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writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr);
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writel(dram->trrd, &emc->t_rrd);
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writel(dram->tmrd, &emc->t_mrd);
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writel(dram->tcdlr, &emc->t_cdlr);
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/* Dynamic refresh */
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writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
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udelay(10);
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/* Force all clocks, enable inverted ck, issue NOP command */
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writel(0x00000193, &emc->control);
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udelay(100);
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/* Keep all clocks enabled, issue a PRECHARGE ALL command */
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writel(0x00000113, &emc->control);
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/* Fast dynamic refresh for at least a few SDRAM ck cycles */
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writel((((128) >> 4) & 0x7FF), &emc->refresh);
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udelay(10);
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/* set correct dynamic refresh timing */
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writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
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udelay(10);
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/* set normal mode to CAS=3 */
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writel(0x00000093, &emc->control);
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readl(EMC_DYCS0_BASE | dram->mode);
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/* set extended mode to all zeroes */
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writel(0x00000093, &emc->control);
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readl(EMC_DYCS0_BASE | dram->emode);
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/* stop forcing clocks, keep inverted clock, issue normal mode */
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writel(0x00000010, &emc->control);
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}
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