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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
76 lines
1.9 KiB
C
76 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91sam9_sdramc.h>
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#include <asm/arch/gpio.h>
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int sdramc_initialize(unsigned int sdram_address, const struct sdramc_reg *p)
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{
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struct sdramc_reg *reg = (struct sdramc_reg *)ATMEL_BASE_SDRAMC;
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unsigned int i;
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/* SDRAM feature must be in the configuration register */
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writel(p->cr, ®->cr);
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/* The SDRAM memory type must be set in the Memory Device Register */
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writel(p->mdr, ®->mdr);
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/*
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* The minimum pause of 200 us is provided to precede any single
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* toggle
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*/
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for (i = 0; i < 1000; i++)
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;
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/* A NOP command is issued to the SDRAM devices */
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writel(AT91_SDRAMC_MODE_NOP, ®->mr);
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writel(0x00000000, sdram_address);
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/* An All Banks Precharge command is issued to the SDRAM devices */
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writel(AT91_SDRAMC_MODE_PRECHARGE, ®->mr);
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writel(0x00000000, sdram_address);
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for (i = 0; i < 10000; i++)
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;
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/* Eight auto-refresh cycles are provided */
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for (i = 0; i < 8; i++) {
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writel(AT91_SDRAMC_MODE_REFRESH, ®->mr);
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writel(0x00000001 + i, sdram_address + 4 + 4 * i);
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}
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/*
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* A Mode Register set (MRS) cyscle is issued to program the
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* SDRAM parameters(TCSR, PASR, DS)
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*/
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writel(AT91_SDRAMC_MODE_LMR, ®->mr);
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writel(0xcafedede, sdram_address + 0x24);
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/*
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* The application must go into Normal Mode, setting Mode
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* to 0 in the Mode Register and perform a write access at
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* any location in the SDRAM.
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*/
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writel(AT91_SDRAMC_MODE_NORMAL, ®->mr);
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writel(0x00000000, sdram_address); /* Perform Normal mode */
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/*
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* Write the refresh rate into the count field in the SDRAMC
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* Refresh Timer Rgister.
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*/
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writel(p->tr, ®->tr);
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return 0;
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}
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