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52f69f818c
This change adds initial support for NXP LPC32x0 SoC series. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Marek Vasut <marek.vasut@gmail.com>
118 lines
2.7 KiB
C
118 lines
2.7 KiB
C
/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <common.h>
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#include <div64.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/io.h>
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static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
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unsigned int get_sys_clk_rate(void)
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{
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if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397)
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return RTC_CLK_FREQUENCY * 397;
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else
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return OSC_CLK_FREQUENCY;
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}
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unsigned int get_hclk_pll_rate(void)
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{
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unsigned long long fin, fref, fcco, fout;
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u32 val, m_div, n_div, p_div;
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/*
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* Valid frequency ranges:
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* 1 * 10^6 <= Fin <= 20 * 10^6
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* 1 * 10^6 <= Fref <= 27 * 10^6
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* 156 * 10^6 <= Fcco <= 320 * 10^6
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*/
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fref = fin = get_sys_clk_rate();
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if (fin > 20000000ULL || fin < 1000000ULL)
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return 0;
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val = readl(&clk->hclkpll_ctrl);
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m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1;
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n_div = ((val & CLK_HCLK_PLL_PREDIV_MASK) >> 9) + 1;
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if (val & CLK_HCLK_PLL_DIRECT)
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p_div = 0;
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else
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p_div = ((val & CLK_HCLK_PLL_POSTDIV_MASK) >> 11) + 1;
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p_div = 1 << p_div;
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if (val & CLK_HCLK_PLL_BYPASS) {
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do_div(fin, p_div);
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return fin;
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}
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do_div(fref, n_div);
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if (fref > 27000000ULL || fref < 1000000ULL)
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return 0;
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fout = fref * m_div;
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if (val & CLK_HCLK_PLL_FEEDBACK) {
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fcco = fout;
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do_div(fout, p_div);
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} else
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fcco = fout * p_div;
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if (fcco > 320000000ULL || fcco < 156000000ULL)
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return 0;
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return fout;
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}
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unsigned int get_hclk_clk_div(void)
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{
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u32 val;
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val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK;
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return 1 << val;
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}
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unsigned int get_hclk_clk_rate(void)
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{
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return get_hclk_pll_rate() / get_hclk_clk_div();
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}
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unsigned int get_periph_clk_div(void)
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{
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u32 val;
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val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK;
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return (val >> 2) + 1;
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}
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unsigned int get_periph_clk_rate(void)
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{
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if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
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return get_sys_clk_rate();
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return get_hclk_pll_rate() / get_periph_clk_div();
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}
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int get_serial_clock(void)
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{
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return get_periph_clk_rate();
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}
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