Melin Tomas d3826fb052 xilinx_xiic: Fix transfer initialisation
Prior to starting a new transfer, conditionally wait for bus to not
be busy.

Reinitialise controller as otherwise operation is not stable.
For reference, see linux kernel
commit 9656eeebf3f1 ("i2c: Revert i2c: xiic: Do not reset controller before every transfer")

hs: Fixed DOS line endings
    added missing '\n'
    Fixed git commit description style

Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
2019-07-09 07:02:11 +02:00
..
2016-08-15 22:12:00 +02:00
2019-05-21 07:52:34 +02:00
2019-02-14 14:31:10 +01:00
2019-03-07 06:20:09 +01:00