Sagar Shrikant Kadam d04a46426b sifive: reset: add DM based reset driver for SiFive SoC's ...

PRCI module within SiFive SoC's has register with which we can
reset the sub-systems within the SoC. The resets to DDR and ethernet
sub systems within FU540-C000 SoC are active low, and are hold low
by default on power-up. Currently these are directly asserted within
prci driver via register read/write.
With the DM based reset driver support here, we bind the reset
driver with clock (prci) driver and assert the reset signals of
both sub-system's appropriately.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>

2020-08-04 09:19:41 +08:00

..

fu540-prci.c

sifive: reset: add DM based reset driver for SiFive SoC's

2020-08-04 09:19:41 +08:00

Kconfig

clk: sifive: Drop GEMGXL clock driver

2019-07-19 14:24:51 +08:00

Makefile

clk: sifive: Drop GEMGXL clock driver

2019-07-19 14:24:51 +08:00