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1009c96f15
Enable driver for Synopsis MIPI DWI3C for the family device agilex5. This driver is migrated from linux version 6.6.37 LTS Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
287 lines
9.1 KiB
C
287 lines
9.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Cadence Design Systems Inc.
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*
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* Author: Boris Brezillon <boris.brezillon@bootlin.com>
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*/
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#ifndef I3C_DEV_H
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#define I3C_DEV_H
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#include <dm/device.h>
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#include <i2c.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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/**
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* enum i3c_error_code - I3C error codes
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*
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* These are the standard error codes as defined by the I3C specification.
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* When -EIO is returned by the i3c_device_do_priv_xfers() or
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* i3c_device_send_hdr_cmds() one can check the error code in
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* &struct_i3c_priv_xfer.err or &struct i3c_hdr_cmd.err to get a better idea of
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* what went wrong.
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*
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* @I3C_ERROR_UNKNOWN: unknown error, usually means the error is not I3C
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* related
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* @I3C_ERROR_M0: M0 error
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* @I3C_ERROR_M1: M1 error
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* @I3C_ERROR_M2: M2 error
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*/
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enum i3c_error_code {
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I3C_ERROR_UNKNOWN = 0,
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I3C_ERROR_M0 = 1,
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I3C_ERROR_M1,
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I3C_ERROR_M2,
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};
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/**
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* enum i3c_hdr_mode - HDR mode ids
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* @I3C_HDR_DDR: DDR mode
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* @I3C_HDR_TSP: TSP mode
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* @I3C_HDR_TSL: TSL mode
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*/
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enum i3c_hdr_mode {
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I3C_HDR_DDR,
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I3C_HDR_TSP,
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I3C_HDR_TSL,
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};
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/**
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* struct i3c_priv_xfer - I3C SDR private transfer
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* @rnw: encodes the transfer direction. true for a read, false for a write
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* @len: transfer length in bytes of the transfer
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* @data: input/output buffer
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* @data.in: input buffer. Must point to a DMA-able buffer
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* @data.out: output buffer. Must point to a DMA-able buffer
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* @err: I3C error code
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*/
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struct i3c_priv_xfer {
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u8 rnw;
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u16 len;
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union {
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void *in;
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const void *out;
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} data;
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enum i3c_error_code err;
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};
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/**
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* enum i3c_dcr - I3C DCR values
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* @I3C_DCR_GENERIC_DEVICE: generic I3C device
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*/
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enum i3c_dcr {
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I3C_DCR_GENERIC_DEVICE = 0,
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};
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#define I3C_PID_MANUF_ID(pid) (((pid) & GENMASK_ULL(47, 33)) >> 33)
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#define I3C_PID_RND_LOWER_32BITS(pid) (!!((pid) & BIT_ULL(32)))
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#define I3C_PID_RND_VAL(pid) ((pid) & GENMASK_ULL(31, 0))
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#define I3C_PID_PART_ID(pid) (((pid) & GENMASK_ULL(31, 16)) >> 16)
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#define I3C_PID_INSTANCE_ID(pid) (((pid) & GENMASK_ULL(15, 12)) >> 12)
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#define I3C_PID_EXTRA_INFO(pid) ((pid) & GENMASK_ULL(11, 0))
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#define I3C_BCR_DEVICE_ROLE(bcr) ((bcr) & GENMASK(7, 6))
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#define I3C_BCR_I3C_SLAVE (0 << 6)
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#define I3C_BCR_I3C_MASTER BIT(6)
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#define I3C_BCR_HDR_CAP BIT(5)
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#define I3C_BCR_BRIDGE BIT(4)
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#define I3C_BCR_OFFLINE_CAP BIT(3)
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#define I3C_BCR_IBI_PAYLOAD BIT(2)
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#define I3C_BCR_IBI_REQ_CAP BIT(1)
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#define I3C_BCR_MAX_DATA_SPEED_LIM BIT(0)
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/* To determine what functionality is present */
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#define I2C_FUNC_I2C 0x00000001
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#define I2C_FUNC_10BIT_ADDR 0x00000002 /* required for I2C_M_TEN */
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#define I2C_FUNC_PROTOCOL_MANGLING 0x00000004 /* required for I2C_M_IGNORE_NAK etc. */
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#define I2C_FUNC_SMBUS_PEC 0x00000008
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#define I2C_FUNC_NOSTART 0x00000010 /* required for I2C_M_NOSTART */
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#define I2C_FUNC_SLAVE 0x00000020
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#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000 /* SMBus 2.0 or later */
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#define I2C_FUNC_SMBUS_QUICK 0x00010000
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#define I2C_FUNC_SMBUS_READ_BYTE 0x00020000
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#define I2C_FUNC_SMBUS_WRITE_BYTE 0x00040000
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#define I2C_FUNC_SMBUS_READ_BYTE_DATA 0x00080000
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#define I2C_FUNC_SMBUS_WRITE_BYTE_DATA 0x00100000
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#define I2C_FUNC_SMBUS_READ_WORD_DATA 0x00200000
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#define I2C_FUNC_SMBUS_WRITE_WORD_DATA 0x00400000
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#define I2C_FUNC_SMBUS_PROC_CALL 0x00800000
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#define I2C_FUNC_SMBUS_READ_BLOCK_DATA 0x01000000 /* required for I2C_M_RECV_LEN */
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#define I2C_FUNC_SMBUS_WRITE_BLOCK_DATA 0x02000000
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#define I2C_FUNC_SMBUS_READ_I2C_BLOCK 0x04000000 /* I2C-like block xfer */
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#define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 0x08000000 /* w/ 1-byte reg. addr. */
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#define I2C_FUNC_SMBUS_HOST_NOTIFY 0x10000000 /* SMBus 2.0 or later */
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#define I2C_FUNC_SMBUS_BYTE (I2C_FUNC_SMBUS_READ_BYTE | \
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I2C_FUNC_SMBUS_WRITE_BYTE)
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#define I2C_FUNC_SMBUS_BYTE_DATA (I2C_FUNC_SMBUS_READ_BYTE_DATA | \
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I2C_FUNC_SMBUS_WRITE_BYTE_DATA)
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#define I2C_FUNC_SMBUS_WORD_DATA (I2C_FUNC_SMBUS_READ_WORD_DATA | \
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I2C_FUNC_SMBUS_WRITE_WORD_DATA)
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#define I2C_FUNC_SMBUS_BLOCK_DATA (I2C_FUNC_SMBUS_READ_BLOCK_DATA | \
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I2C_FUNC_SMBUS_WRITE_BLOCK_DATA)
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#define I2C_FUNC_SMBUS_I2C_BLOCK (I2C_FUNC_SMBUS_READ_I2C_BLOCK | \
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I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)
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#define I2C_FUNC_SMBUS_EMUL (I2C_FUNC_SMBUS_QUICK | \
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I2C_FUNC_SMBUS_BYTE | \
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I2C_FUNC_SMBUS_BYTE_DATA | \
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I2C_FUNC_SMBUS_WORD_DATA | \
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I2C_FUNC_SMBUS_PROC_CALL | \
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I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | \
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I2C_FUNC_SMBUS_I2C_BLOCK | \
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I2C_FUNC_SMBUS_PEC)
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/**
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* struct i3c_device_info - I3C device information
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* @pid: Provisional ID
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* @bcr: Bus Characteristic Register
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* @dcr: Device Characteristic Register
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* @static_addr: static/I2C address
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* @dyn_addr: dynamic address
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* @hdr_cap: supported HDR modes
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* @max_read_ds: max read speed information
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* @max_write_ds: max write speed information
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* @max_ibi_len: max IBI payload length
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* @max_read_turnaround: max read turn-around time in micro-seconds
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* @max_read_len: max private SDR read length in bytes
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* @max_write_len: max private SDR write length in bytes
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*
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* These are all basic information that should be advertised by an I3C device.
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* Some of them are optional depending on the device type and device
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* capabilities.
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* For each I3C slave attached to a master with
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* i3c_master_add_i3c_dev_locked(), the core will send the relevant CCC command
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* to retrieve these data.
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*/
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struct i3c_device_info {
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u64 pid;
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u8 bcr;
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u8 dcr;
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u8 static_addr;
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u8 dyn_addr;
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u8 hdr_cap;
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u8 max_read_ds;
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u8 max_write_ds;
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u8 max_ibi_len;
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u32 max_read_turnaround;
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u16 max_read_len;
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u16 max_write_len;
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};
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/*
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* I3C device internals are kept hidden from I3C device users. It's just
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* simpler to refactor things when everything goes through getter/setters, and
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* I3C device drivers should not have to worry about internal representation
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* anyway.
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*/
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struct i3c_device;
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/* These macros should be used to i3c_device_id entries. */
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#define I3C_MATCH_MANUF_AND_PART (I3C_MATCH_MANUF | I3C_MATCH_PART)
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#define I3C_DEVICE(_manufid, _partid, _drvdata) \
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{ \
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.match_flags = I3C_MATCH_MANUF_AND_PART, \
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.manuf_id = _manufid, \
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.part_id = _partid, \
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.data = _drvdata, \
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}
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#define I3C_DEVICE_EXTRA_INFO(_manufid, _partid, _info, _drvdata) \
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{ \
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.match_flags = I3C_MATCH_MANUF_AND_PART | \
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I3C_MATCH_EXTRA_INFO, \
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.manuf_id = _manufid, \
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.part_id = _partid, \
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.extra_info = _info, \
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.data = _drvdata, \
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}
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#define I3C_CLASS(_dcr, _drvdata) \
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{ \
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.match_flags = I3C_MATCH_DCR, \
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.dcr = _dcr, \
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}
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/**
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* struct i3c_driver - I3C device driver
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* @driver: inherit from driver
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* @probe: I3C device probe method
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* @remove: I3C device remove method
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* @id_table: I3C device match table. Will be used by the framework to decide
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* which device to bind to this driver
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*/
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struct i3c_driver {
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struct driver driver;
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int (*probe)(struct i3c_device *dev);
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void (*remove)(struct i3c_device *dev);
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const struct i3c_device_id *id_table;
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};
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static inline struct i3c_driver *drv_to_i3cdrv(const struct driver *drv)
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{
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return container_of(drv, struct i3c_driver, driver);
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}
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struct udevice *i3cdev_to_dev(struct i3c_device *i3cdev);
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struct i3c_device *dev_to_i3cdev(struct udevice *dev);
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const struct i3c_device_id *
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i3c_device_match_id(struct i3c_device *i3cdev,
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const struct i3c_device_id *id_table);
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/**
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* module_i3c_i2c_driver() - Register a module providing an I3C and an I2C
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* driver
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* @__i3cdrv: the I3C driver to register
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* @__i2cdrv: the I3C driver to register
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*
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* Provide generic init/exit functions that simply register/unregister an I3C
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* and an I2C driver.
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* This macro can be used even if CONFIG_I3C is disabled, in this case, only
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* the I2C driver will be registered.
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* Should be used by any driver that does not require extra init/cleanup steps.
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*/
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#define module_i3c_i2c_driver(__i3cdrv, __i2cdrv) \
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module_driver(__i3cdrv, \
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i3c_i2c_driver_register, \
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i3c_i2c_driver_unregister)
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void i3c_device_get_info(struct i3c_device *dev, struct i3c_device_info *info);
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struct i3c_ibi_payload {
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unsigned int len;
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const void *data;
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};
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/**
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* struct i3c_ibi_setup - IBI setup object
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* @max_payload_len: maximum length of the payload associated to an IBI. If one
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* IBI appears to have a payload that is bigger than this
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* number, the IBI will be rejected.
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* @num_slots: number of pre-allocated IBI slots. This should be chosen so that
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* the system never runs out of IBI slots, otherwise you'll lose
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* IBIs.
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* @handler: IBI handler, every time an IBI is received. This handler is called
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* in a workqueue context. It is allowed to sleep and send new
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* messages on the bus, though it's recommended to keep the
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* processing done there as fast as possible to avoid delaying
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* processing of other queued on the same workqueue.
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*
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* Temporary structure used to pass information to i3c_device_request_ibi().
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* This object can be allocated on the stack since i3c_device_request_ibi()
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* copies every bit of information and do not use it after
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* i3c_device_request_ibi() has returned.
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*/
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struct i3c_ibi_setup {
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unsigned int max_payload_len;
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unsigned int num_slots;
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void (*handler)(struct i3c_device *dev,
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const struct i3c_ibi_payload *payload);
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};
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#endif /* I3C_DEV_H */
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