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1a2621bab8
The R0P7752C00000RZ board has SH7752, 512MB DDR3-SDRAM, SPI ROM, Gigabit Ethernet, and eMMC. This patch supports the following functions: - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
117 lines
2.6 KiB
C
117 lines
2.6 KiB
C
/*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License. See the file "COPYING.LIB" in the main
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* directory of this archive for more details.
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*/
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#include <common.h>
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#define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE
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#define CONFIG_SPI_ADDR 0x00000000
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#define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN
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#define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE
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#define SPIWDMADR 0xFE001018
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#define SPIWDMCNTR 0xFE001020
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#define SPIDMCOR 0xFE001028
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#define SPIDMINTSR 0xFE001188
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#define SPIDMINTMR 0xFE001190
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#define SPIDMINTSR_DMEND 0x00000004
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#define TBR 0xFE002000
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#define RBR 0xFE002000
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#define CR1 0xFE002008
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#define CR2 0xFE002010
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#define CR3 0xFE002018
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#define CR4 0xFE002020
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/* CR1 */
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#define SPI_TBE 0x80
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#define SPI_TBF 0x40
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#define SPI_RBE 0x20
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#define SPI_RBF 0x10
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#define SPI_PFONRD 0x08
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#define SPI_SSDB 0x04
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#define SPI_SSD 0x02
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#define SPI_SSA 0x01
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/* CR2 */
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#define SPI_RSTF 0x80
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#define SPI_LOOPBK 0x40
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#define SPI_CPOL 0x20
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#define SPI_CPHA 0x10
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#define SPI_L1M0 0x08
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/* CR4 */
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#define SPI_TBEI 0x80
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#define SPI_TBFI 0x40
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#define SPI_RBEI 0x20
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#define SPI_RBFI 0x10
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#define SPI_SpiS0 0x02
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#define SPI_SSS 0x01
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#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
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#define spi_read(addr) (*(volatile unsigned long *)(addr))
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/* M25P80 */
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#define M25_READ 0x03
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#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
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static void __uses_spiboot2 spi_reset(void)
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{
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int timeout = 0x00100000;
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/* Make sure the last transaction is finalized */
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spi_write(0x00, CR3);
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spi_write(0x02, CR1);
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while (!(spi_read(CR4) & SPI_SpiS0)) {
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if (timeout-- < 0)
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break;
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}
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spi_write(0x00, CR1);
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spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
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spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
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spi_write(0, SPIDMCOR);
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}
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static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
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unsigned long len)
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{
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spi_write(M25_READ, TBR);
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spi_write((addr >> 16) & 0xFF, TBR);
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spi_write((addr >> 8) & 0xFF, TBR);
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spi_write(addr & 0xFF, TBR);
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spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
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spi_write((unsigned long)buf, SPIWDMADR);
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spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
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spi_write(1, SPIDMCOR);
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spi_write(0xff, CR3);
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spi_write(spi_read(CR1) | SPI_SSDB, CR1);
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spi_write(spi_read(CR1) | SPI_SSA, CR1);
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while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
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;
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/* Nagate SP0-SS0 */
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spi_write(0, CR1);
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}
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void __uses_spiboot2 spiboot_main(void)
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{
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void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
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spi_reset();
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spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
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CONFIG_SPI_LENGTH);
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_start();
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}
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