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	This patch adds the NAND SPL framework needed to boot i.MX31 boards from NAND. It has been tested on a i.MX31 PDK board with large page NAND. Small page NANDs should work as well, but this has not been tested. Note: The i.MX31 NFC uses a non-standard layout for large page NANDs, whether this is compatible with a particular setup depends on how the NAND device is programmed by the flash programmer (e.g. JTAG debugger). The patch is based on the work by Maxim Artamonov. Signed-off-by: Maxim Artamonov <scn1874@yandex.ru> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
		
			
				
	
	
		
			260 lines
		
	
	
		
			6.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			260 lines
		
	
	
		
			6.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * (C) Copyright 2009
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 * Magnus Lilja <lilja.magnus@gmail.com>
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 *
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 * (C) Copyright 2008
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 * Maxim Artamonov, <scn1874 at yandex.ru>
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 *
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 * (C) Copyright 2006-2008
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 * Stefan Roese, DENX Software Engineering, sr at denx.de.
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 of
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 * the License, or (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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 * MA 02111-1307 USA
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 */
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#include <common.h>
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#include <nand.h>
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#include <asm-arm/arch/mx31-regs.h>
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#include <asm/io.h>
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#include <fsl_nfc.h>
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static struct fsl_nfc_regs *nfc;
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static void nfc_wait_ready(void)
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{
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	uint32_t tmp;
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	while (!(readw(&nfc->nand_flash_config2) & NFC_INT))
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		;
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	/* Reset interrupt flag */
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	tmp = readw(&nfc->nand_flash_config2);
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	tmp &= ~NFC_INT;
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	writew(tmp, &nfc->nand_flash_config2);
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}
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static void nfc_nand_init(void)
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{
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	/* unlocking RAM Buff */
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	writew(0x2, &nfc->configuration);
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	/* hardware ECC checking and correct */
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	writew(NFC_ECC_EN, &nfc->nand_flash_config1);
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}
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static void nfc_nand_command(unsigned short command)
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{
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	writew(command, &nfc->flash_cmd);
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	writew(NFC_CMD, &nfc->nand_flash_config2);
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	nfc_wait_ready();
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}
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static void nfc_nand_page_address(unsigned int page_address)
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{
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	unsigned int page_count;
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	writew(0x00, &nfc->flash_cmd);
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	writew(NFC_ADDR, &nfc->nand_flash_config2);
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	nfc_wait_ready();
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	/* code only for 2kb flash */
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	if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) {
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		writew(0x00, &nfc->flash_add);
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		writew(NFC_ADDR, &nfc->nand_flash_config2);
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		nfc_wait_ready();
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	}
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	page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
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	if (page_address <= page_count) {
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		page_count--; /* transform 0x01000000 to 0x00ffffff */
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		do {
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			writew(page_address & 0xff, &nfc->flash_add);
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			writew(NFC_ADDR, &nfc->nand_flash_config2);
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			nfc_wait_ready();
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			page_address = page_address >> 8;
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			page_count = page_count >> 8;
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		} while (page_count);
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	}
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}
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static void nfc_nand_data_output(void)
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{
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	int i;
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	/*
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	 * The NAND controller requires four output commands for
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	 * large page devices.
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	 */
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	for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) {
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		writew(NFC_ECC_EN, &nfc->nand_flash_config1);
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		writew(i, &nfc->buffer_address); /* read in i:th buffer */
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		writew(NFC_OUTPUT, &nfc->nand_flash_config2);
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		nfc_wait_ready();
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	}
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}
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static int nfc_nand_check_ecc(void)
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{
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	return readw(&nfc->ecc_status_result);
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}
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static int nfc_read_page(unsigned int page_address, unsigned char *buf)
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{
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	int i;
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	u32 *src;
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	u32 *dst;
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	writew(0, &nfc->buffer_address); /* read in first 0 buffer */
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	nfc_nand_command(NAND_CMD_READ0);
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	nfc_nand_page_address(page_address);
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	if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800)
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		nfc_nand_command(NAND_CMD_READSTART);
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	nfc_nand_data_output(); /* fill the main buffer 0 */
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	if (nfc_nand_check_ecc())
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		return -1;
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	src = &nfc->main_area0[0];
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	dst = (u32 *)buf;
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	/* main copy loop from NAND-buffer to SDRAM memory */
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	for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 4); i++) {
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		writel(readl(src), dst);
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		src++;
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		dst++;
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	}
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	return 0;
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}
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static int is_badblock(int pagenumber)
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{
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	int page = pagenumber;
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	u32 badblock;
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	u32 *src;
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	/* Check the first two pages for bad block markers */
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	for (page = pagenumber; page < pagenumber + 2; page++) {
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		writew(0, &nfc->buffer_address); /* read in first 0 buffer */
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		nfc_nand_command(NAND_CMD_READ0);
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		nfc_nand_page_address(page);
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		if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800)
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			nfc_nand_command(NAND_CMD_READSTART);
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		nfc_nand_data_output(); /* fill the main buffer 0 */
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		src = &nfc->spare_area0[0];
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		/*
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		 * IMPORTANT NOTE: The nand flash controller uses a non-
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		 * standard layout for large page devices. This can
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		 * affect the position of the bad block marker.
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		 */
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		/* Get the bad block marker */
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		badblock = readl(&src[CONFIG_SYS_NAND_BAD_BLOCK_POS / 4]);
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		badblock >>= 8 * (CONFIG_SYS_NAND_BAD_BLOCK_POS % 4);
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		badblock &= 0xff;
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		/* bad block marker verify */
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		if (badblock != 0xff)
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			return 1; /* potential bad block */
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	}
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	return 0;
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}
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static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
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{
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	int i;
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	unsigned int page;
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	unsigned int maxpages = CONFIG_SYS_NAND_SIZE /
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				CONFIG_SYS_NAND_PAGE_SIZE;
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	nfc = (void *)NFC_BASE_ADDR;
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	nfc_nand_init();
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	/* Convert to page number */
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	page = from / CONFIG_SYS_NAND_PAGE_SIZE;
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	i = 0;
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	while (i < (size / CONFIG_SYS_NAND_PAGE_SIZE)) {
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		if (nfc_read_page(page, buf) < 0)
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			return -1;
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		page++;
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		i++;
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		buf = buf + CONFIG_SYS_NAND_PAGE_SIZE;
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		/*
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		 * Check if we have crossed a block boundary, and if so
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		 * check for bad block.
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		 */
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		if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
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			/*
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			 * Yes, new block. See if this block is good. If not,
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			 * loop until we find i good block.
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			 */
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			while (is_badblock(page)) {
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				page = page + CONFIG_SYS_NAND_PAGE_COUNT;
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				/* Check i we've reached the end of flash. */
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				if (page >= maxpages)
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					return -1;
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			}
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		}
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	}
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	return 0;
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}
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/*
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 * The main entry for NAND booting. It's necessary that SDRAM is already
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 * configured and available since this code loads the main U-Boot image
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 * from NAND into SDRAM and starts it from there.
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 */
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void nand_boot(void)
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{
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	__attribute__((noreturn)) void (*uboot)(void);
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	nfc = (void *)NFC_BASE_ADDR;
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	/*
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	 * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
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	 * be aligned to full pages
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	 */
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	if (!nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
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		       (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
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		/* Copy from NAND successful, start U-boot */
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		uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
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		uboot();
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	} else {
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		/* Unrecoverable error when copying from NAND */
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		hang();
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	}
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}
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/*
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 * Called in case of an exception.
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 */
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void hang(void)
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{
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	/* Loop forever */
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	while (1) ;
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}
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