Andre Przywara 869d396191 sunxi: mmc: add support for Allwinner A523 MMC mod clock
The Allwinner A523 SoC has a slightly changed mod clock, where the P
factor, formerly a shift value, is now a second divider value.
Also the input clock is not PLL_PERIPH0 (600MHz) anymore, but
PLL_PERIPH0_400M (for MMC0/1), so adjust the input rate calculation
accordingly. MMC2 has a different set of parents, so the input clock
is 800 MHz there.
Adjust for all of this.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-07-27 22:57:35 +01:00
..
2024-01-29 22:35:02 -05:00
2025-06-02 17:26:16 -06:00
2024-12-11 08:36:24 +01:00