Rick Chen 61ce84b2cf riscv: cache: use CCTL to flush d-cache ...

Use CCTL command to do d-cache write back
and invalidate instead of fence.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

2019-09-03 09:31:03 +08:00

..

ax25

riscv: cache: use CCTL to flush d-cache

2019-09-03 09:31:03 +08:00

generic

riscv: add SPL support

2019-08-26 16:07:42 +08:00

cpu.c

riscv: add run mode configuration for SPL

2019-08-26 16:07:42 +08:00

Makefile

riscv: Move trap handler codes to mtrap.S

2018-12-18 09:56:27 +08:00

mtrap.S

riscv: Return to previous privilege level after trap handling

2018-12-18 09:56:27 +08:00

start.S

riscv: update fix_rela_dyn

2019-09-03 09:30:41 +08:00

u-boot-spl.lds

riscv: add SPL support

2019-08-26 16:07:42 +08:00

u-boot.lds

riscv: Make start.S available for all targets

2018-10-03 17:48:14 +08:00