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862b4a0f32
Implement translation table support for all the variations of Apple's DART IOMMU that can be found on Apple's M1 and M2 SoCs. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
320 lines
8.8 KiB
C
320 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <iommu.h>
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#include <lmb.h>
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#include <memalign.h>
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#include <asm/io.h>
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#define DART_PARAMS2 0x0004
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#define DART_PARAMS2_BYPASS_SUPPORT BIT(0)
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#define DART_T8020_TLB_CMD 0x0020
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#define DART_T8020_TLB_CMD_FLUSH BIT(20)
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#define DART_T8020_TLB_CMD_BUSY BIT(2)
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#define DART_T8020_TLB_SIDMASK 0x0034
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#define DART_T8020_ERROR 0x0040
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#define DART_T8020_ERROR_ADDR_LO 0x0050
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#define DART_T8020_ERROR_ADDR_HI 0x0054
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#define DART_T8020_CONFIG 0x0060
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#define DART_T8020_CONFIG_LOCK BIT(15)
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#define DART_T8020_SID_ENABLE 0x00fc
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#define DART_T8020_TCR_BASE 0x0100
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#define DART_T8020_TCR_TRANSLATE_ENABLE BIT(7)
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#define DART_T8020_TCR_BYPASS_DART BIT(8)
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#define DART_T8020_TCR_BYPASS_DAPF BIT(12)
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#define DART_T8020_TTBR_BASE 0x0200
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#define DART_T8020_TTBR_VALID BIT(31)
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#define DART_T8110_PARAMS4 0x000c
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#define DART_T8110_PARAMS4_NSID_MASK (0x1ff << 0)
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#define DART_T8110_TLB_CMD 0x0080
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#define DART_T8110_TLB_CMD_BUSY BIT(31)
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#define DART_T8110_TLB_CMD_FLUSH_ALL BIT(8)
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#define DART_T8110_ERROR 0x0100
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#define DART_T8110_ERROR_MASK 0x0104
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#define DART_T8110_ERROR_ADDR_LO 0x0170
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#define DART_T8110_ERROR_ADDR_HI 0x0174
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#define DART_T8110_PROTECT 0x0200
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#define DART_T8110_PROTECT_TTBR_TCR BIT(0)
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#define DART_T8110_SID_ENABLE_BASE 0x0c00
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#define DART_T8110_TCR_BASE 0x1000
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#define DART_T8110_TCR_BYPASS_DAPF BIT(2)
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#define DART_T8110_TCR_BYPASS_DART BIT(1)
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#define DART_T8110_TCR_TRANSLATE_ENABLE BIT(0)
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#define DART_T8110_TTBR_BASE 0x1400
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#define DART_T8110_TTBR_VALID BIT(0)
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#define DART_SID_ENABLE(priv, idx) \
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((priv)->sid_enable_base + 4 * (idx))
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#define DART_TCR(priv, sid) ((priv)->tcr_base + 4 * (sid))
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#define DART_TTBR(priv, sid, idx) \
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((priv)->ttbr_base + 4 * (priv)->nttbr * (sid) + 4 * (idx))
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#define DART_TTBR_SHIFT 12
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#define DART_ALL_STREAMS(priv) ((1U << (priv)->nsid) - 1)
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#define DART_PAGE_SIZE SZ_16K
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#define DART_PAGE_MASK (DART_PAGE_SIZE - 1)
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#define DART_L1_TABLE 0x3
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#define DART_L2_INVAL 0
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#define DART_L2_VALID BIT(0)
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#define DART_L2_FULL_PAGE BIT(1)
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#define DART_L2_START(addr) ((((addr) & DART_PAGE_MASK) >> 2) << 52)
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#define DART_L2_END(addr) ((((addr) & DART_PAGE_MASK) >> 2) << 40)
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struct apple_dart_priv {
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void *base;
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struct lmb lmb;
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u64 *l1, *l2;
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int bypass, shift;
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dma_addr_t dvabase;
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dma_addr_t dvaend;
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int nsid;
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int nttbr;
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int sid_enable_base;
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int tcr_base;
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u32 tcr_translate_enable;
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u32 tcr_bypass;
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int ttbr_base;
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u32 ttbr_valid;
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void (*flush_tlb)(struct apple_dart_priv *priv);
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};
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static void apple_dart_t8020_flush_tlb(struct apple_dart_priv *priv)
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{
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dsb();
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writel(DART_ALL_STREAMS(priv), priv->base + DART_T8020_TLB_SIDMASK);
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writel(DART_T8020_TLB_CMD_FLUSH, priv->base + DART_T8020_TLB_CMD);
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while (readl(priv->base + DART_T8020_TLB_CMD) &
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DART_T8020_TLB_CMD_BUSY)
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continue;
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}
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static void apple_dart_t8110_flush_tlb(struct apple_dart_priv *priv)
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{
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dsb();
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writel(DART_T8110_TLB_CMD_FLUSH_ALL,
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priv->base + DART_T8110_TLB_CMD_FLUSH_ALL);
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while (readl(priv->base + DART_T8110_TLB_CMD) &
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DART_T8110_TLB_CMD_BUSY)
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continue;
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}
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static dma_addr_t apple_dart_map(struct udevice *dev, void *addr, size_t size)
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{
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struct apple_dart_priv *priv = dev_get_priv(dev);
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phys_addr_t paddr, dva;
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phys_size_t psize, off;
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int i, idx;
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if (priv->bypass)
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return (phys_addr_t)addr;
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paddr = ALIGN_DOWN((phys_addr_t)addr, DART_PAGE_SIZE);
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off = (phys_addr_t)addr - paddr;
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psize = ALIGN(size + off, DART_PAGE_SIZE);
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dva = lmb_alloc(&priv->lmb, psize, DART_PAGE_SIZE);
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idx = dva / DART_PAGE_SIZE;
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for (i = 0; i < psize / DART_PAGE_SIZE; i++) {
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priv->l2[idx + i] = (paddr >> priv->shift) | DART_L2_VALID |
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DART_L2_START(0LL) | DART_L2_END(~0LL);
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paddr += DART_PAGE_SIZE;
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}
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flush_dcache_range((unsigned long)&priv->l2[idx],
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(unsigned long)&priv->l2[idx + i]);
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priv->flush_tlb(priv);
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return dva + off;
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}
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static void apple_dart_unmap(struct udevice *dev, dma_addr_t addr, size_t size)
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{
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struct apple_dart_priv *priv = dev_get_priv(dev);
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phys_addr_t dva;
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phys_size_t psize;
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int i, idx;
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if (priv->bypass)
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return;
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dva = ALIGN_DOWN(addr, DART_PAGE_SIZE);
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psize = size + (addr - dva);
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psize = ALIGN(psize, DART_PAGE_SIZE);
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idx = dva / DART_PAGE_SIZE;
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for (i = 0; i < psize / DART_PAGE_SIZE; i++)
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priv->l2[idx + i] = DART_L2_INVAL;
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flush_dcache_range((unsigned long)&priv->l2[idx],
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(unsigned long)&priv->l2[idx + i]);
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priv->flush_tlb(priv);
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lmb_free(&priv->lmb, dva, psize);
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}
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static struct iommu_ops apple_dart_ops = {
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.map = apple_dart_map,
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.unmap = apple_dart_unmap,
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};
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static int apple_dart_probe(struct udevice *dev)
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{
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struct apple_dart_priv *priv = dev_get_priv(dev);
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dma_addr_t addr;
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phys_addr_t l2;
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int ntte, nl1, nl2;
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int sid, i;
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u32 params2, params4;
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priv->base = dev_read_addr_ptr(dev);
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if (!priv->base)
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return -EINVAL;
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if (device_is_compatible(dev, "apple,t8110-dart")) {
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params4 = readl(priv->base + DART_T8110_PARAMS4);
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priv->nsid = params4 & DART_T8110_PARAMS4_NSID_MASK;
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priv->nttbr = 1;
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priv->sid_enable_base = DART_T8110_SID_ENABLE_BASE;
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priv->tcr_base = DART_T8110_TCR_BASE;
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priv->tcr_translate_enable = DART_T8110_TCR_TRANSLATE_ENABLE;
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priv->tcr_bypass =
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DART_T8110_TCR_BYPASS_DAPF | DART_T8110_TCR_BYPASS_DART;
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priv->ttbr_base = DART_T8110_TTBR_BASE;
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priv->ttbr_valid = DART_T8110_TTBR_VALID;
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priv->flush_tlb = apple_dart_t8110_flush_tlb;
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} else {
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priv->nsid = 16;
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priv->nttbr = 4;
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priv->sid_enable_base = DART_T8020_SID_ENABLE;
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priv->tcr_base = DART_T8020_TCR_BASE;
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priv->tcr_translate_enable = DART_T8020_TCR_TRANSLATE_ENABLE;
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priv->tcr_bypass =
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DART_T8020_TCR_BYPASS_DAPF | DART_T8020_TCR_BYPASS_DART;
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priv->ttbr_base = DART_T8020_TTBR_BASE;
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priv->ttbr_valid = DART_T8020_TTBR_VALID;
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priv->flush_tlb = apple_dart_t8020_flush_tlb;
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}
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if (device_is_compatible(dev, "apple,t6000-dart") ||
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device_is_compatible(dev, "apple,t8110-dart"))
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priv->shift = 4;
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priv->dvabase = DART_PAGE_SIZE;
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priv->dvaend = SZ_4G - DART_PAGE_SIZE;
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lmb_init(&priv->lmb);
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lmb_add(&priv->lmb, priv->dvabase, priv->dvaend - priv->dvabase);
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/* Disable translations. */
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for (sid = 0; sid < priv->nsid; sid++)
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writel(0, priv->base + DART_TCR(priv, sid));
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/* Remove page tables. */
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for (sid = 0; sid < priv->nsid; sid++) {
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for (i = 0; i < priv->nttbr; i++)
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writel(0, priv->base + DART_TTBR(priv, sid, i));
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}
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priv->flush_tlb(priv);
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params2 = readl(priv->base + DART_PARAMS2);
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if (params2 & DART_PARAMS2_BYPASS_SUPPORT) {
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for (sid = 0; sid < priv->nsid; sid++) {
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writel(priv->tcr_bypass,
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priv->base + DART_TCR(priv, sid));
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}
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priv->bypass = 1;
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return 0;
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}
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ntte = DIV_ROUND_UP(priv->dvaend, DART_PAGE_SIZE);
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nl2 = DIV_ROUND_UP(ntte, DART_PAGE_SIZE / sizeof(u64));
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nl1 = DIV_ROUND_UP(nl2, DART_PAGE_SIZE / sizeof(u64));
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priv->l2 = memalign(DART_PAGE_SIZE, nl2 * DART_PAGE_SIZE);
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memset(priv->l2, 0, nl2 * DART_PAGE_SIZE);
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flush_dcache_range((unsigned long)priv->l2,
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(unsigned long)priv->l2 + nl2 * DART_PAGE_SIZE);
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priv->l1 = memalign(DART_PAGE_SIZE, nl1 * DART_PAGE_SIZE);
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memset(priv->l1, 0, nl1 * DART_PAGE_SIZE);
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l2 = (phys_addr_t)priv->l2;
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for (i = 0; i < nl2; i++) {
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priv->l1[i] = (l2 >> priv->shift) | DART_L1_TABLE;
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l2 += DART_PAGE_SIZE;
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}
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flush_dcache_range((unsigned long)priv->l1,
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(unsigned long)priv->l1 + nl1 * DART_PAGE_SIZE);
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/* Install page tables. */
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for (sid = 0; sid < priv->nsid; sid++) {
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addr = (phys_addr_t)priv->l1;
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for (i = 0; i < nl1; i++) {
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writel(addr >> DART_TTBR_SHIFT | priv->ttbr_valid,
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priv->base + DART_TTBR(priv, sid, i));
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addr += DART_PAGE_SIZE;
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}
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}
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priv->flush_tlb(priv);
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/* Enable all streams. */
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for (i = 0; i < priv->nsid / 32; i++)
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writel(~0, priv->base + DART_SID_ENABLE(priv, i));
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/* Enable translations. */
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for (sid = 0; sid < priv->nsid; sid++) {
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writel(priv->tcr_translate_enable,
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priv->base + DART_TCR(priv, sid));
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}
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return 0;
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}
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static int apple_dart_remove(struct udevice *dev)
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{
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struct apple_dart_priv *priv = dev_get_priv(dev);
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int sid, i;
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/* Disable translations. */
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for (sid = 0; sid < priv->nsid; sid++)
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writel(0, priv->base + DART_TCR(priv, sid));
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/* Remove page tables. */
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for (sid = 0; sid < priv->nsid; sid++) {
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for (i = 0; i < priv->nttbr; i++)
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writel(0, priv->base + DART_TTBR(priv, sid, i));
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}
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priv->flush_tlb(priv);
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return 0;
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}
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static const struct udevice_id apple_dart_ids[] = {
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{ .compatible = "apple,t8103-dart" },
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{ .compatible = "apple,t6000-dart" },
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{ .compatible = "apple,t8110-dart" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(apple_dart) = {
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.name = "apple_dart",
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.id = UCLASS_IOMMU,
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.of_match = apple_dart_ids,
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.priv_auto = sizeof(struct apple_dart_priv),
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.ops = &apple_dart_ops,
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.probe = apple_dart_probe,
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.remove = apple_dart_remove,
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.flags = DM_FLAG_OS_PREPARE
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};
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