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afc1ce8288
Documents and READMEs for NDS32 architecture. It patch also provides usage of SoC AG101 and board ADP-AG101. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
56 lines
1.4 KiB
Plaintext
56 lines
1.4 KiB
Plaintext
N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
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Features
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========
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CPU Core
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- 16-/32-bit mixable instruction format.
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- 32 general-purpose 32-bit registers.
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- 8-stage pipeline.
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- Dynamic branch prediction.
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- 32/64/128/256 BTB.
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- Return address stack (RAS).
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- Vector interrupts for internal/external.
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interrupt controller with 6 hardware interrupt signals.
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- 3 HW-level nested interruptions.
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- User and super-user mode support.
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- Memory-mapped I/O.
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- Address space up to 4GB.
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Memory Management Unit
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- TLB
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- 4/8-entry fully associative iTLB/dTLB.
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- 32/64/128-entry 4-way set-associati.ve main TLB.
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- TLB locking support
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- Optional hardware page table walker.
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- Two groups of page size support.
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- 4KB & 1MB.
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- 8KB & 1MB.
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Memory Subsystem
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- I & D cache.
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- Virtually indexed and physically tagged.
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- Cache size: 8KB/16KB/32KB/64KB.
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- Cache line size: 16B/32B.
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- Set associativity: 2-way, 4-way or direct-mapped.
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- Cache locking support.
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- I & D local memory (LM).
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- Size: 4KB to 1MB.
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- Bank numbers: 1 or 2.
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- Optional 1D/2D DMA engine.
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- Internal or external to CPU core.
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Bus Interface
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- Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
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- Synchronous High speed memory port.
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(HSMP): 0, 1 or 2 ports.
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Debug
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- JTAG debug interface.
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- Embedded debug module (EDM).
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- Optional embedded program tracer interface.
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Miscellaneous
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- Programmable data endian control.
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- Performance monitoring mechanism.
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