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Add clock controller driver for sophgo cv1800b SoC Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
75 lines
2.0 KiB
C
75 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
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*
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*/
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#ifndef __clk_SOPHGO_PLL_H__
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#define __clk_SOPHGO_PLL_H__
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#include <clk.h>
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#include "clk-common.h"
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struct cv1800b_clk_synthesizer {
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struct cv1800b_clk_regbit en;
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struct cv1800b_clk_regbit clk_half;
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u32 ctrl;
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u32 set;
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};
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struct cv1800b_clk_ipll {
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struct clk clk;
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const char *name;
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const char *parent_name;
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void __iomem *base;
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u32 pll_reg;
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struct cv1800b_clk_regbit pll_pwd;
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struct cv1800b_clk_regbit pll_status;
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};
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struct cv1800b_clk_fpll {
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struct cv1800b_clk_ipll ipll;
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struct cv1800b_clk_synthesizer syn;
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};
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#define CV1800B_IPLL(_id, _name, _parent_name, _pll_reg, _pll_pwd_offset, \
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_pll_pwd_shift, _pll_status_offset, _pll_status_shift, \
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_flags) \
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{ \
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.clk = { \
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.id = CV1800B_CLK_ID_TRANSFORM(_id), \
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.flags = _flags, \
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}, \
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.name = _name, \
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.parent_name = _parent_name, \
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.pll_reg = _pll_reg, \
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.pll_pwd = CV1800B_CLK_REGBIT(_pll_pwd_offset, _pll_pwd_shift), \
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.pll_status = CV1800B_CLK_REGBIT(_pll_status_offset, \
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_pll_status_shift), \
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}
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#define CV1800B_FPLL(_id, _name, _parent_name, _pll_reg, _pll_pwd_offset, \
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_pll_pwd_shift, _pll_status_offset, _pll_status_shift, \
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_syn_en_offset, _syn_en_shift, _syn_clk_half_offset, \
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_syn_clk_half_shift, _syn_ctrl_offset, _syn_set_offset, \
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_flags) \
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{ \
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.ipll = CV1800B_IPLL(_id, _name, _parent_name, _pll_reg, \
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_pll_pwd_offset, _pll_pwd_shift, \
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_pll_status_offset, _pll_status_shift, \
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_flags), \
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.syn = { \
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.en = CV1800B_CLK_REGBIT(_syn_en_offset, _syn_en_shift),\
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.clk_half = CV1800B_CLK_REGBIT(_syn_clk_half_offset, \
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_syn_clk_half_shift), \
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.ctrl = _syn_ctrl_offset, \
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.set = _syn_set_offset, \
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}, \
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}
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extern const struct clk_ops cv1800b_ipll_ops;
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extern const struct clk_ops cv1800b_fpll_ops;
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#endif /* __clk_SOPHGO_PLL_H__ */
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