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55c4a6db54
Add Retronix R-Car V4H Sparrow Hawk board based on Renesas R-Car V4H ES3.0
(R8A779G3) SoC. This is a single-board computer with single gigabit ethernet,
DSI-to-eDP bridge, DSI and two CSI2 interfaces, audio codec, two CANFD ports,
micro SD card slot, USB PD supply, USB 3.0 ports, M.2 Key-M slot for NVMe SSD,
debug UART and JTAG.
DT is imported from Linux next commit:
a719915e76f2 ("arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
144 lines
3.7 KiB
C
144 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
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*/
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#include <asm/io.h>
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#include <compiler.h>
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#include <dbsc5.h>
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#include <spl.h>
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#if defined(CONFIG_XPL_BUILD)
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static const struct renesas_dbsc5_board_config
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renesas_v4h_sparrowhawk_8g_6400_dbsc5_board_config = {
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/* RENESAS V4H Sparrow Hawk (64Gbit 1rank) */
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.bdcfg_phyvalid = 0xF,
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.bdcfg_vref_r = 0x0,
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.bdcfg_vref_w = 0x0,
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.bdcfg_vref_ca = 0x0,
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.bdcfg_rfm_chk = true,
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.ch = {
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[0] = {
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.bdcfg_ddr_density = { 0x06, 0xFF },
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.bdcfg_ca_swap = 0x04506132,
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.bdcfg_dqs_swap = 0x01,
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.bdcfg_dq_swap = { 0x26157084, 0x12306854 },
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.bdcfg_dm_swap = { 0x03, 0x07 },
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.bdcfg_cs_swap = 0x10
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},
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[1] = {
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.bdcfg_ddr_density = { 0x06, 0xFF },
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.bdcfg_ca_swap = 0x02431065,
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.bdcfg_dqs_swap = 0x10,
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.bdcfg_dq_swap = { 0x56782314, 0x70423856 },
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.bdcfg_dm_swap = { 0x00, 0x01 },
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.bdcfg_cs_swap = 0x10
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},
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[2] = {
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.bdcfg_ddr_density = { 0x06, 0xFF },
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.bdcfg_ca_swap = 0x02150643,
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.bdcfg_dqs_swap = 0x10,
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.bdcfg_dq_swap = { 0x58264031, 0x40587236 },
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.bdcfg_dm_swap = { 0x07, 0x01 },
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.bdcfg_cs_swap = 0x10
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},
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[3] = {
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.bdcfg_ddr_density = { 0x06, 0xFF },
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.bdcfg_ca_swap = 0x01546230,
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.bdcfg_dqs_swap = 0x01,
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.bdcfg_dq_swap = { 0x45761328, 0x68023745 },
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.bdcfg_dm_swap = { 0x00, 0x01 },
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.bdcfg_cs_swap = 0x10
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}
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}
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};
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static const struct renesas_dbsc5_board_config
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renesas_v4h_sparrowhawk_16g_5500_dbsc5_board_config = {
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/* RENESAS V4H Sparrow Hawk (64Gbit 2rank) */
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.bdcfg_phyvalid = 0xF,
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.bdcfg_vref_r = 0x0,
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.bdcfg_vref_w = 0x0,
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.bdcfg_vref_ca = 0x0,
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.bdcfg_rfm_chk = true,
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.ch = {
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[0] = {
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.bdcfg_ddr_density = { 0x06, 0x06 },
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.bdcfg_ca_swap = 0x04506132,
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.bdcfg_dqs_swap = 0x01,
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.bdcfg_dq_swap = { 0x26157084, 0x12306854 },
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.bdcfg_dm_swap = { 0x03, 0x07 },
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.bdcfg_cs_swap = 0x10
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},
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[1] = {
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.bdcfg_ddr_density = { 0x06, 0x06 },
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.bdcfg_ca_swap = 0x02431065,
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.bdcfg_dqs_swap = 0x10,
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.bdcfg_dq_swap = { 0x56782314, 0x70423856 },
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.bdcfg_dm_swap = { 0x00, 0x01 },
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.bdcfg_cs_swap = 0x10
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},
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[2] = {
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.bdcfg_ddr_density = { 0x06, 0x06 },
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.bdcfg_ca_swap = 0x02150643,
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.bdcfg_dqs_swap = 0x10,
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.bdcfg_dq_swap = { 0x58264031, 0x40587236 },
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.bdcfg_dm_swap = { 0x07, 0x01 },
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.bdcfg_cs_swap = 0x10
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},
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[3] = {
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.bdcfg_ddr_density = { 0x06, 0x06 },
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.bdcfg_ca_swap = 0x01546230,
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.bdcfg_dqs_swap = 0x01,
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.bdcfg_dq_swap = { 0x45761328, 0x68023745 },
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.bdcfg_dm_swap = { 0x00, 0x01 },
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.bdcfg_cs_swap = 0x10
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}
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}
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};
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const struct renesas_dbsc5_board_config *
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dbsc5_get_board_data(struct udevice *dev, const u32 modemr0)
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{
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/*
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* MD[19] is used to discern between 5500 Mbps and 6400 Mbps operation.
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*
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* Boards with 1 rank of DRAM can operate at 6400 Mbps, those are the
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* Sparrow Hawk boards with 8 GiB of DRAM. Boards with 2 ranks of DRAM
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* are limited to 5500 Mbps operation, those are the boards with 16 GiB
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* of DRAM.
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*
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* Use MD[19] setting to discern 8 GiB and 16 GiB DRAM Sparrow Hawk
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* board variants from each other automatically.
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*/
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if (modemr0 & BIT(19))
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return &renesas_v4h_sparrowhawk_16g_5500_dbsc5_board_config;
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else
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return &renesas_v4h_sparrowhawk_8g_6400_dbsc5_board_config;
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}
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#endif
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#define RST_MODEMR0 0xe6160000
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DECLARE_GLOBAL_DATA_PTR;
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void renesas_dram_init_banksize(void)
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{
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const u32 modemr0 = readl(RST_MODEMR0);
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int bank;
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/* 8 GiB device, do nothing. */
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if (!(modemr0 & BIT(19)))
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return;
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/* 16 GiB device, adjust memory map. */
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for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
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if (gd->bd->bi_dram[bank].start == 0x480000000ULL)
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gd->bd->bi_dram[bank].size = 0x180000000ULL;
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else if (gd->bd->bi_dram[bank].start == 0x600000000ULL)
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gd->bd->bi_dram[bank].size = 0x200000000ULL;
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}
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}
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