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9efcb10a09
AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU for the first stage bootloader execution, namely SPL. This patch implements the preliminary base to successfully run SPL on this RV32-based MCU to the console banner message. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
73 lines
1.6 KiB
C
73 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) Aspeed Technology Inc.
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*/
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#include <asm/io.h>
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#include <asm/arch/sli.h>
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#include <asm/arch/scu.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#define SLI_POLL_TIMEOUT_US 100
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static void sli_clear_interrupt_status(uint32_t base)
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{
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writel(-1, (void *)base + SLI_INTR_STATUS);
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}
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static int sli_wait(uint32_t base, uint32_t mask)
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{
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uint32_t value;
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sli_clear_interrupt_status(base);
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do {
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value = readl((void *)base + SLI_INTR_STATUS);
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if (value & SLI_INTR_RX_ERRORS)
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return -1;
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} while ((value & mask) != mask);
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return 0;
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}
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static int sli_wait_suspend(uint32_t base)
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{
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return sli_wait(base, SLI_INTR_TX_SUSPEND | SLI_INTR_RX_SUSPEND);
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}
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/*
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* CPU die --- downstream pads ---> I/O die
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* CPU die <--- upstream pads ----- I/O die
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*
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* US/DS PAD[3:0] : SLIM[3:0]
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* US/DS PAD[5:4] : SLIH[1:0]
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* US/DS PAD[7:6] : SLIV[1:0]
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*/
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int sli_init(void)
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{
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uint32_t value;
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/* The following training sequence is designed for AST2700A0 */
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value = FIELD_GET(SCU1_REVISION_HWID, readl(SCU1_REVISION));
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if (value)
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return 0;
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/* Return if SLI had been calibrated */
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value = readl((void *)SLIH_IOD_BASE + SLI_CTRL_III);
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value = FIELD_GET(SLI_CLK_SEL, value);
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if (value) {
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debug("SLI has been initialized\n");
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return 0;
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}
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/* 25MHz PAD delay for AST2700A0 */
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value = SLI_RX_PHY_LAH_SEL_NEG | SLI_TRANS_EN | SLI_CLEAR_BUS;
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writel(value, (void *)SLIH_IOD_BASE + SLI_CTRL_I);
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writel(value, (void *)SLIM_IOD_BASE + SLI_CTRL_I);
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writel(value | SLIV_RAW_MODE, (void *)SLIV_IOD_BASE + SLI_CTRL_I);
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sli_wait_suspend(SLIH_IOD_BASE);
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sli_wait_suspend(SLIH_CPU_BASE);
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return 0;
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}
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