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ab0e1c11a9
Add bloblist support to total_comput platform for passing data from TF-A using the firmware handoff framework. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
122 lines
2.3 KiB
C
122 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2020 Arm Limited
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* Usama Arif <usama.arif@arm.com>
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*/
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#include <config.h>
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#include <dm.h>
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#include <dm/platform_data/serial_pl01x.h>
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#include <cpu_func.h>
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#include <env.h>
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#include <linux/sizes.h>
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#include <asm/armv8/mmu.h>
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#include <asm/global_data.h>
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#include <asm/system.h>
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/* +1 is end of list which needs to be empty */
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#define TC_MEM_MAP_MAX (1 + CONFIG_NR_DRAM_BANKS + 1)
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static struct mm_region total_compute_mem_map[TC_MEM_MAP_MAX] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}
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};
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struct mm_region *mem_map = total_compute_mem_map;
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#ifdef CONFIG_OF_HAS_PRIOR_STAGE
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/*
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* Push the variable into the .data section so that it
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* does not get cleared later.
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*/
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unsigned long __section(".data") fw_dtb_pointer;
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int board_fdt_blob_setup(void **fdtp)
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{
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if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC)
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return -ENXIO;
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*fdtp = (void *)fw_dtb_pointer;
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return 0;
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}
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#endif
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int misc_init_r(void)
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{
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size_t base;
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#ifdef CONFIG_OF_HAS_PRIOR_STAGE
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if (!env_get("fdt_addr_r"))
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env_set_hex("fdt_addr_r", fw_dtb_pointer);
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#endif
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if (!env_get("kernel_addr_r")) {
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/*
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* The kernel has to be 2M aligned and the first 64K at the
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* start of SDRAM is reserved for DTB.
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*/
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base = gd->ram_base + SZ_2M;
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assert(IS_ALIGNED(base, SZ_2M));
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env_set_hex("kernel_addr_r", base);
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}
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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return fdtdec_setup_mem_size_base();
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}
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int dram_init_banksize(void)
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{
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return fdtdec_setup_memory_banksize();
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}
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void build_mem_map(void)
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{
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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/*
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* The first node is for I/O device, start from node 1 for
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* updating DRAM info.
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*/
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mem_map[i + 1].virt = gd->bd->bi_dram[i].start;
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mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
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mem_map[i + 1].size = gd->bd->bi_dram[i].size;
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mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE;
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}
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}
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void enable_caches(void)
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{
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build_mem_map();
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icache_enable();
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dcache_enable();
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}
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u64 get_page_table_size(void)
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{
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return SZ_256K;
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}
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/* Nothing to be done here as handled by PSCI interface */
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void reset_cpu(void)
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{
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}
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