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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
23 lines
594 B
C
23 lines
594 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017 Intel Corporation.
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* Take from coreboot project file of the same name
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*/
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#include <asm/intel_regs.h>
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#include <asm/io.h>
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#include <asm/arch/systemagent.h>
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void enable_bios_reset_cpl(void)
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{
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/*
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* Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
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* that BIOS has initialised memory and power management
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*
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* The FSP-S does not do this. If we leave this as zero then I believe
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* the power-aware interrupts don't work in Linux, and CPU 0 always gets
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* the interrupt.
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*/
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setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3);
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}
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