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ce8f49ece2
TH1520 SoC ships several IOPMPs protecting various on-chip peripherals. They must be configured before accessing the peripherals. Let's initialize them in SPL harts_early_init(). Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
97 lines
2.3 KiB
C
97 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
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*/
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#include <asm/arch/iopmp.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <linux/sizes.h>
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#include <log.h>
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#include <init.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define TH1520_SUBSYS_CLK (void __iomem *)(0xffff011000 + 0x220)
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#define TH1520_SUBSYS_CLK_VO_EN BIT(2)
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#define TH1520_SUBSYS_CLK_VI_EN BIT(1)
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#define TH1520_SUBSYS_CLK_DSP_EN BIT(0)
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#define TH1520_SUBSYS_RST (void __iomem *)(0xffff015000 + 0x220)
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#define TH1520_SUBSYS_RST_VP_N BIT(3)
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#define TH1520_SUBSYS_RST_VO_N BIT(2)
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#define TH1520_SUBSYS_RST_VI_N BIT(1)
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#define TH1520_SUBSYS_RST_DSP_N BIT(0)
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int spl_dram_init(void)
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{
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int ret;
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struct udevice *dev;
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ret = fdtdec_setup_mem_size_base();
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if (ret) {
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printf("failed to setup memory size and base: %d\n", ret);
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return ret;
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}
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/* DDR init */
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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printf("DRAM init failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static void __iomem *th1520_iopmp_regs[] = {
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TH1520_IOPMP_EMMC,
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TH1520_IOPMP_SDIO0,
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TH1520_IOPMP_SDIO1,
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TH1520_IOPMP_USB0,
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TH1520_IOPMP_AO,
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TH1520_IOPMP_AUD,
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TH1520_IOPMP_CHIP_DBG,
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TH1520_IOPMP_EIP120I,
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TH1520_IOPMP_EIP120II,
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TH1520_IOPMP_EIP120III,
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TH1520_IOPMP_ISP0,
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TH1520_IOPMP_ISP1,
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TH1520_IOPMP_DW200,
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TH1520_IOPMP_VIPRE,
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TH1520_IOPMP_VENC,
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TH1520_IOPMP_VDEC,
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TH1520_IOPMP_G2D,
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TH1520_IOPMP_FCE,
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TH1520_IOPMP_NPU,
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TH1520_IOPMP_DPU0,
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TH1520_IOPMP_DPU1,
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TH1520_IOPMP_GPU,
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TH1520_IOPMP_GMAC1,
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TH1520_IOPMP_GMAC2,
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TH1520_IOPMP_DMAC,
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TH1520_IOPMP_TEE_DMAC,
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TH1520_IOPMP_DSP0,
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TH1520_IOPMP_DSP1,
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};
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void harts_early_init(void)
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{
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int i;
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/*
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* Set IOPMPs to the default attribute, allowing the application
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* processor to access various peripherals. Subsystem clocks should be
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* enabled and resets should be deasserted ahead of time, or the HART
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* will hang when configuring corresponding IOPMP entries.
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*/
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setbits_le32(TH1520_SUBSYS_CLK, TH1520_SUBSYS_CLK_VO_EN |
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TH1520_SUBSYS_CLK_VI_EN |
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TH1520_SUBSYS_CLK_DSP_EN);
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setbits_le32(TH1520_SUBSYS_RST, TH1520_SUBSYS_RST_VP_N |
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TH1520_SUBSYS_RST_VO_N |
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TH1520_SUBSYS_RST_VI_N |
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TH1520_SUBSYS_RST_DSP_N);
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for (i = 0; i < ARRAY_SIZE(th1520_iopmp_regs); i++)
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writel(TH1520_IOPMP_DEFAULT_ATTR, th1520_iopmp_regs[i]);
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}
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