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Introduce the SoC-specific code and corresponding Kconfig entries for TH1520 SoC. Following features are implemented for TH1520, - Cache enable/disable through customized CSR - Invalidation of customized PMP entries - DRAM driver probing for SPL Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
22 lines
553 B
C
22 lines
553 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2025 Yao Zi <ziyao@disroot.org>
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*
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* TH1520 SoC has a set of undocumented customized PMP registers that are
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* configured through MMIO operation. It must be disabled before entering
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* the DRAM region, or an exception will be raised.
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*/
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#include <asm/io.h>
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#include <cpu_func.h>
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#define TH1520_PMP_BASE (void *)0xffdc020000
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void th1520_invalidate_pmp(void)
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{
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/* Invalidate the PMP configuration as in vendor U-Boot code */
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writel(0x0, TH1520_PMP_BASE + 0x0);
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invalidate_icache_all();
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}
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