mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-08-19 05:31:31 +02:00
5fe9ced355
Introduce the SoC-specific code and corresponding Kconfig entries for TH1520 SoC. Following features are implemented for TH1520, - Cache enable/disable through customized CSR - Invalidation of customized PMP entries - DRAM driver probing for SPL Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
33 lines
573 B
C
33 lines
573 B
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (c) 2025 Yao Zi <ziyao@disroot.org>
|
|
*/
|
|
|
|
#include <asm/io.h>
|
|
#include <cpu_func.h>
|
|
#include <linux/bitops.h>
|
|
|
|
#define CSR_MHCR 0x7c1
|
|
#define CSR_MHCR_IE BIT(0)
|
|
#define CSR_MHCR_DE BIT(1)
|
|
|
|
void icache_enable(void)
|
|
{
|
|
csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE);
|
|
}
|
|
|
|
void dcache_enable(void)
|
|
{
|
|
csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_DE);
|
|
}
|
|
|
|
int icache_status(void)
|
|
{
|
|
return (csr_read(CSR_MHCR) & CSR_MHCR_IE) != 0;
|
|
}
|
|
|
|
int dcache_status(void)
|
|
{
|
|
return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0;
|
|
}
|