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38742c7485
Adds support for Analog Devices' SC598-SOM-EZKIT board. Includes: - CONFIG options common to all SC5xx SoCs - SoC specific configs in mach-sc5xx/Kconfig - SPL config options in common/spl/Kconfig - Memory Map for SPL - Necessary board-specific init functions - Board-specific Kconfig and environment in board/adi/ - Memory configuration Co-developed-by: Greg Malysa <greg.malysa@timesys.com> Signed-off-by: Greg Malysa <greg.malysa@timesys.com> Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Co-developed-by: Trevor Woerner <twoerner@gmail.com> Signed-off-by: Trevor Woerner <twoerner@gmail.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com>
123 lines
3.3 KiB
C
123 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* (C) Copyright 2024 - Analog Devices, Inc.
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*
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* Written and/or maintained by Timesys Corporation
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*
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* Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
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* Contact: Greg Malysa <greg.malysa@timesys.com>
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*/
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#include <asm/io.h>
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#include <asm/armv8/mmu.h>
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#include <asm/arch-adi/sc5xx/sc5xx.h>
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#include <asm/arch-adi/sc5xx/spl.h>
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#define REG_TSGENWR0_CNTCR 0x310AE000
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#define REG_PADS0_PCFG0 0x31004604
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#define REG_RCU0_BCODE 0x3108C028
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#define REG_SPU0_SECUREP_START 0x3108BA00
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#define REG_SPU0_WP_START 0x3108B400
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#define REG_SPU0_SECUREC0 0x3108B980
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#define REG_SCB5_SPI2_OSPI_REMAP 0x30400000
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#define BITM_SCB5_SPI2_OSPI_REMAP_REMAP 0x00000003
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#define ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0 0x00000001
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static struct mm_region sc598_mem_map[] = {
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{
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/* Peripherals */
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* DDR */
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = sc598_mem_map;
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adi_rom_boot_fn adi_rom_boot = (adi_rom_boot_fn)0x000000e4;
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void sc5xx_enable_rgmii(void)
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{
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writel((readl(REG_PADS0_PCFG0) | 0xc), REG_PADS0_PCFG0);
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// Set dw for little endian operation as well
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writel(readl(REG_PADS0_PCFG0) & ~(1 << 19), REG_PADS0_PCFG0);
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writel(readl(REG_PADS0_PCFG0) & ~(1 << 20), REG_PADS0_PCFG0);
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}
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void sc59x_remap_ospi(void)
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{
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clrsetbits_le32(REG_SCB5_SPI2_OSPI_REMAP,
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BITM_SCB5_SPI2_OSPI_REMAP_REMAP,
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ENUM_SCB5_SPI2_OSPI_REMAP_OSPI0);
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}
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/**
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* SPU/SMPU configuration is the default for permissive access from non-secure
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* EL1. If TFA and OPTEE are configured, they run *after* this code, as the
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* current boot flow is SPL -> TFA -> OPTEE -> Proper -> Linux, and will
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* be expected to configure peripheral security correctly. If they are not
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* configured, then this permissive setting will allow Linux (which always
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* runs in NS EL1) to control all access to these peripherals. Without it,
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* the peripherals would simply be unavailable in a non-security build,
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* which is not OK.
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*/
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void sc5xx_soc_init(void)
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{
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phys_addr_t smpus[] = {
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0x31007800, //SMPU0
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0x31083800, //SMPU2
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0x31084800, //SMPU3
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0x31085800, //SMPU4
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0x31086800, //SMPU5
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0x31087800, //SMPU6
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0x310A0800, //SMPU9
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0x310A1800, //SMPU11
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0x31012800, //SMPU12
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};
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size_t i;
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// Enable coresight timer
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writel(1, REG_TSGENWR0_CNTCR);
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//Do not rerun preboot routine --
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// Without this, hardware resets triggered by RCU0_CTL:SYSRST
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// lead to a deadlock somewhere in the boot ROM
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writel(0x200, REG_RCU0_BCODE);
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/* Alter outstanding transactions property of A55*/
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writel(0x1, 0x30643108); /* SCB6 A55 M0 Ib.fn Mod */
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isb();
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/* configure DDR prefetch behavior, per ADI */
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writel(0x1, 0x31076000);
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/* configure smart mode, per ADI */
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writel(0x1307, 0x31076004);
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// Disable SPU and SPU WP registers
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sc5xx_disable_spu0(REG_SPU0_SECUREP_START, REG_SPU0_SECUREP_START + 4*213);
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sc5xx_disable_spu0(REG_SPU0_WP_START, REG_SPU0_WP_START + 4*213);
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/* configure smpus permissively */
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for (i = 0; i < ARRAY_SIZE(smpus); ++i)
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writel(0x500, smpus[i]);
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sc5xx_enable_ns_sharc_access(REG_SPU0_SECUREC0);
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}
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