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9d81a9ff99
When support for the Renesas RZ/G2L SoC was added, the GICR base address
for CPU1 was accidentally used. We should instead supply the GICR base
address for CPU0 so that interrupts are correctly configured for the
CPU core that U-Boot is actually using.
Fixes: 387d4275ab ("arm: rmobile: Add basic RZ/G2L family support")
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
14 lines
278 B
C
14 lines
278 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* RZ/G2L SoC Family support.
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* Copyright (C) 2023 Renesas Electronics Corporation
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*/
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#ifndef __ASM_ARCH_RZG2L_H
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#define __ASM_ARCH_RZG2L_H
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#define GICD_BASE 0x11900000
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#define GICR_BASE 0x11940000
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#endif /* __ASM_ARCH_RZG2L_H */
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